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M4A5-64/32-65JNC

Description
EE PLD, 6.5ns, CMOS, PQCC44, PLASTIC, LCC-44
CategoryProgrammable logic    Programmable logic devices   
File Size3MB,62 Pages
ManufacturerLattice
Websitehttp://www.latticesemi.com
Environmental Compliance  
Download Datasheet Parametric View All

M4A5-64/32-65JNC Overview

EE PLD, 6.5ns, CMOS, PQCC44, PLASTIC, LCC-44

M4A5-64/32-65JNC Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerLattice
Parts packaging codeLCC
package instructionQCCJ,
Contacts44
Reach Compliance Codecompliant
ECCN codeEAR99
Is SamacsysN
maximum clock frequency95.2 MHz
JESD-30 codeS-PQCC-J44
JESD-609 codee3
length16.5862 mm
Humidity sensitivity level3
Dedicated input times
Number of I/O lines32
Number of terminals44
Maximum operating temperature70 °C
Minimum operating temperature
organize0 DEDICATED INPUTS, 32 I/O
Output functionMACROCELL
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Package shapeSQUARE
Package formCHIP CARRIER
Peak Reflow Temperature (Celsius)245
Programmable logic typeEE PLD
propagation delay6.5 ns
Certification statusNot Qualified
Maximum seat height4.57 mm
Maximum supply voltage5.25 V
Minimum supply voltage4.75 V
Nominal supply voltage5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperature40
width16.5862 mm
Base Number Matches1
MACH 4 CPLD Family
High Performance EE CMOS
Programmable Logic
FEATURES
x
High-performance, EE CMOS 3.3-V & 5-V CPLD families
x
Flexible architecture for rapid logic designs
I
MAC nclude
s
H
Adv
anc 4A Fam
e In
form ily
atio
n
x
x
x
x
x
x
x
x
— Excellent First-Time-Fit
TM
and refit feature
— SpeedLocking
TM
performance for guaranteed fixed timing
— Central, input and output switch matrices for 100% routability and 100% pin-out retention
High speed
— 5.0ns t
PD
Commercial and 7.5ns t
PD
Industrial
— 182MHz f
CNT
32 to 512 macrocells; 32 to 768 registers
44 to 352 pins in PLCC, PQFP, TQFP, BGA, or fpBGA packages
Advanced capabilities for easy system integration
— 3.3-V & 5-V JEDEC-compliant operations
— JTAG (IEEE 1149.1) compliant for boundary scan testing
— 3.3-V & 5-V JTAG in-system programming
— PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)
— Safe for mixed supply voltage system designs
— Programmable pull-up or Bus-Friendly
TM
inputs and I/Os
— Hot-socketing
— Programmable security bit
— Individual output slew rate control
Flexible architecture for a wide range of design styles
— D/T registers and latches
— Synchronous or asynchronous mode
— Dedicated input registers
— Programmable polarity
— Reset/ preset swapping
Advanced EE CMOS process provides high-performance, cost-effective solutions
Supported by Vantis DesignDirect
TM
software for rapid logic development
— Supports HDL design methodologies with results optimized for Vantis
— Flexibility to adapt to user requirements
— Software partnerships that ensure customer success
Lattice/Vantis and third-party hardware programming support
— Lattice/VantisPRO
TM
(formerly known as MACHPRO
®
) software for in-system programmability
support on PCs and automated test equipment
— Programming support on all major programmers including Data I/O, BP Microsystems, Advin,
and System General
Publication#
17466
Amendment/0
Rev:
J
Issue Date:
May 1999
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