Each block can be programmed and erased up to 100,000 cycles with ECC (error correction code) on. To extend the lifetime of
NAND flash devices, the implementation of an ECC is mandatory.
The chip supports CE# don't care function. This function allows the direct download of the code from the NAND flash memory device
by a microcontroller, since the CE# transitions do not stop the read operation.
The devices have a Read Cache feature that improves the read throughput for large files. During cache reading, the devices load
the data in a cache register while the previous data is transferred to the I/O buffers to be read.
Like all other 2-kB page NAND flash devices, a program operation typically writes 2112 bytes (×8), or 1056 words (×16) in 200 µs
and an erase operation can typically be performed in 2 ms (S34ML01G1) on a 128-kB block (×8) or 64-kword block (×16). In
addition, thanks to multiplane architecture, it is possible to program two pages at a time (one per plane) or to erase two blocks at a
time (again, one per plane). The multiplane architecture allows program time to be reduced by 40% and erase time to be reduced by
50%.
In multiplane operations, data in the page can be read out at 25 ns cycle time per byte. The I/O pins serve as the ports for command
and address input as well as data input/output. This interface allows a reduced pin count and easy migration towards different
densities, without any rearrangement of the footprint.
Commands, Data, and Addresses are asynchronously introduced using CE#, WE#, ALE, and CLE control pins.
The on-chip Program/Erase Controller automates all read, program, and erase functions including pulse repetition, where required,
and internal verification and margining of data. A WP# pin is available to provide hardware protection against program and erase
operations.
The output pin R/B# (open drain buffer) signals the status of the device during each operation. It identifies if the program/erase/read
controller is currently active. The use of an open-drain output allows the Ready/Busy pins from several memories to connect to a
single pull-up resistor. In a system with multiple memories the
R/B# pins can be connected all together to provide a global status signal.
The Reprogram function allows the optimization of defective block management — when a Page Program operation fails the data
can be directly programmed in another page inside the same array section without the time consuming serial data insertion phase.
The Copy Back operation automatically executes embedded error detection operation: 1-bit error out of every 528 bytes (×8) or 256
words (×16) can be detected. With this feature it is no longer necessary to use an external mechanism to detect Copy Back
operation errors.
Multiplane Copy Back is also supported. Data read out after Copy Back Read (both for single and multiplane cases) is allowed.
In addition, Cache Program and Multiplane Cache Program operations improve the programing throughput by programing data
using the cache register.
The devices provide two innovative features: Page Reprogram and Multiplane Page Reprogram. The Page Reprogram re-programs
one page. Normally, this operation is performed after a failed Page Program operation. Similarly, the Multiplane Page Reprogram re-
programs two pages in parallel, one per plane. The first page must be in the first plane while the second page must be in the second
plane. The Multiplane Page Reprogram operation is performed after a failed Multiplane Page Program operation. The Page
Reprogram and Multiplane Page Reprogram guarantee improved performance, since data insertion can be omitted during re-
program operations.
Note:
The S34ML01G1 device does not support EDC.
Document Number: 002-00676 Rev. *T
Page 3 of 73
S34ML01G1
S34ML02G1, S34ML04G1
The devices come with an OTP (one time programmable) area, which is a restricted access area where sensitive data/code can be
stored permanently. This security feature is subject to an NDA (non-disclosure agreement) and is, therefore, not described in the
data sheet. For more details, contact your nearest Cypress sales office.
Density (bits)
Device
Main
S34ML01G1
128M x 8
64M x 16
256M x 8
128M x 16
512M x 8
256M x 16
Spare
4M x 8
2M x 16
8M x 8
4M x 16
16M x 8
8M x 16
1
Number of Planes
Number of Blocks
per Plane
1024
EDC Support
No
S34ML02G1
2
1024
Yes
S34ML04G1
2
2048
Yes
1.1
Logic Diagram
Figure 1.1
Logic Diagram
VCC
CE#
WE#
RE#
ALE
CLE
WP#
I/O0~I/O7
R/B#
VSS
Table 1.1
Signal Names
I/O7 - I/O0
(×8)
Data Input / Outputs
I/O8 - I/O15
(×16)
CLE
ALE
CE#
RE#
WE#
WP#
R/B#
VCC
VSS
NC
Command Latch Enable
Address Latch Enable
Chip Enable
Read Enable
Write Enable
Write Protect
Read/Busy
Power Supply
Ground
Not Connected
Document Number: 002-00676 Rev. *T
Page 4 of 73
S34ML01G1
S34ML02G1, S34ML04G1
1.2
Connection Diagram
Figure 1.2
48-Pin TSOP1 Contact ×8, ×16 Devices
x16
NC
NC
NC
NC
NC
NC
R/B#
RE#
CE#
NC
NC
VCC
VSS
NC
NC
CLE
ALE
WE#
WP#
NC
NC
NC
NC
NC
x8
NC
NC
NC
NC
NC
NC
R/B#
RE#
CE#
NC
NC
VCC
VSS
NC
NC
CLE
ALE
WE#
WP#
NC
NC
NC
NC
NC
x8
x16
1
48
12
13
NAND Flash
TSOP1
37
36
VSS
(1)
NC
NC
NC
I/O7
I/O6
I/O5
I/O4
NC
VCC
(1)
NC
VCC
VSS
NC
VCC
(1)
24
25
VSS
I/O15
I/O14
I/O13
I/O7
I/O6
I/O5
I/O4
I/O12
VCC
NC
VCC
VSS
NC
VCC
I/011
NC
I/O3
I/O3
I/O2
I/O2
I/O1
I/O1
I/O0
I/O0
I/O10
NC
I/O9
NC
I/O8
NC
VSS
(1)
VSS
Note:
1. These pins should be connected to power supply or ground (as designated) following the ONFI specification, however they might not be bonded internally.
Figure 1.3
63-BGA Contact, ×8 Device (Balls Down, Top View)
A1
NC
B1
NC
C3
WP#
D3
VCC
(1)
E3
NC
F3
NC
G3
NC
H3
NC
J3
NC
K3
V
SS
L1
NC
M1
NC
L2
NC
M2
NC
C4
ALE
D4
RE#
E4
NC
F4
NC
G4
VCC
(1)
H4
I/O0
J4
I/O1
K4
I/O2
C5
VSS
D5
CLE
E5
NC
F5
NC
G5
NC
H5
NC
J5
NC
K5
I/O3
C6
CE#
D6
NC
E6
NC
F6
NC
G6
NC
H6
NC
J6
V
CC
K6
I/O4
C7
WE#
D7
NC
E7
NC
F7
VSS
(1)
G7
NC
H7
NC
J7
I/O5
K7
I/O6
C8
RB#
D8
NC
E8
NC
F8
NC
G8
NC
H8
V
cc
J8
I/O7
K8
V
SS
L9
NC
M9
NC
L10
NC
M10
NC
A2
NC
A9
NC
B9
NC
A10
NC
B10
NC
Note:
1. These pins should be connected to power supply or ground (as designated) following the ONFI specification, however they might not be bonded internally.
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