FUJITSU SEMICONDUCTOR
DATA SHEET
DS501-00051-1v0-E
Memory FRAM
64 K (8 K
8) Bit SPI
MB85RS64T
■
DESCRIPTION
MB85RS64T is a FRAM (Ferroelectric Random Access Memory) chip in a configuration of 8,192 words
8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the nonvolatile
memory cells.
MB85RS64T adopts the Serial Peripheral Interface (SPI).
The MB85RS64T is able to retain data without using a back-up battery, as is needed for SRAM.
The memory cells used in the MB85RS64T can be used for 10
13
read/write operations, which is a significant
improvement over the number of read and write operations supported by Flash memory and E
2
PROM.
MB85RS64T does not take long time to write data like Flash memories or E
2
PROM, and MB85RS64T takes
no wait time.
■
FEATURES
• Bit configuration : 8,192 words
8 bits
• Serial Peripheral Interface : SPI (Serial Peripheral Interface)
Correspondent to SPI mode 0 (0, 0) and mode 3 (1, 1)
• Operating frequency : 10 MHz (Max)
• High endurance : 10
13
times / byte
• Data retention
: 10 years (
85
C)
• Operating power supply voltage : 1.8 V to 3.6 V
• Low power consumption : Operating power supply current 0.8 mA (Max@10 MHz)
Standby current 9
A
(Typ)
• Operation ambient temperature range :
40
C
to +85
C
• Package
: 8-pin plastic SOP (FPT-8P-M02)
8-pin plastic SON (LLC-8P-M04)
RoHS compliant
Copyright 2017FUJITSU SEMICONDUCTOR LIMITED
2017.12
MB85RS64T
■
PIN ASSIGNMENT
(TOP VIEW)
(TOP VIEW)
8
VDD
A0
1
2
3
4
8
7
6
5
VDD
WP
SCL
SDA
CS
1
SO
2
7
HOLD
A1
A2
WP
3
6
SCK
VSS
VSS
4
5
SI
(LCC-8P-M04)
(FPT-8P-M02)
■
PIN FUNCTIONAL DESCRIPTIONS
Pin No. Pin Name
Functional description
Chip Select pin
This is an input pin to make chip select. When CS is the “H” level, device is in deselect
(standby) status and SO becomes High-Z. Inputs from other pins are ignored at this time.
When CS is the “L” level, device is in select (active) status. CS has to be the “L” level
before inputting op-code.
Write Protect pin
This is a pin to control writing to a status register. The writing of status register (see “■
STATUS REGISTER”) is protected in related with WP and WPEN. See “■WRITING
PROTECT” for detail.
Hold pin
This pin is used to interrupt serial input/output without making chip deselect. When
HOLD is the “L” level, hold operation is activated, SO becomes High-Z, and SCK and SI
become don’t care. While the hold operation, CS shall be retained the “L” level.
Serial Clock pin
This is a clock input pin to input/output serial data. SI is loaded synchronously to a rising
edge, SO is output synchronously to a falling edge.
Serial Data Input pin
This is an input pin of serial data. This inputs op-code, address, and writing data.
Serial Data Output pin
This is an output pin of serial data. Reading data of FRAM memory cell array and status
register are output. This is High-Z during standby.
Supply Voltage pin
Ground pin
1
CS
3
WP
7
HOLD
6
SCK
5
SI
2
8
4
SO
VDD
VSS
2
DS501-00051-1v0-E
MB85RS64T
■
BLOCK DIAGRAM
Serial-Parallel Converter
Row Decoder
SI
FRAM Cell Array
8,192
✕
8
CS
Address Counter
SCK
Control Circuit
FRAM
Status Register
HOLD
Column Decoder/Sense Amp/
Write Amp
WP
Data Register
SO
Parallel-Serial Converter
DS501-00051-1v0-E
3
MB85RS64T
■
SPI MODE
MB85RS64T corresponds to the SPI mode 0 (CPOL
½
0, CPHA
½
0) , and SPI mode 3 (CPOL
½
1, CPHA
½
1) .
CS
SCK
SI
7
MSB
6
5
4
3
2
1
0
LSB
SPI Mode 0
CS
SCK
SI
7
MSB
6
5
4
3
2
1
0
LSB
SPI Mode 3
4
DS501-00051-1v0-E
MB85RS64T
■
SERIAL PERIPHERAL INTERFACE (SPI)
MB85RS64T works as a slave of SPI. More than 2 devices can be connected by using microcontroller
equipped with SPI port. By using a microcontroller not equipped with SPI port, SI and SO can be bus
connected to use.
SCK
MOSI
MISO
SO
SI
SCK
SO
SI
SCK
SPI
Microcontroller
MB85RS64T
CS
SS1
SS2
HOLD1
HOLD2
HOLD
MB85RS64T
CS
HOLD
MOSI : Master Out Slave In
MISO : Master In Slave Out
SS
: Slave Select
System Configuration with SPI Port
SO
SI
SCK
Microcontroller
MB85RS64T
CS
HOLD
System Configuration without SPI Port
DS501-00051-1v0-E
5
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