FUJITSU SEMICONDUCTOR
DATA SHEET
DS501-00024-4v0-E
Memory FRAM
4 M (256 K × 16) Bit
MB85R4M2T
DESCRIPTIONS
The MB85R4M2T is an FRAM (Ferroelectric Random Access Memory) chip consisting of 262,144 words
× 16 bits of nonvolatile memory cells fabricated using ferroelectric process and silicon gate CMOS process
technologies.
The MB85R4M2T is able to retain data without using a back-up battery, as is needed for SRAM.
The memory cells used in the MB85R4M2T can be used for 10
13
read/write operations, which is a
significant improvement over the number of read and write operations supported by Flash memory and
E2PROM. The MB85R4M2T uses a pseudo-SRAM interface.
FEATURES
• Bit configuration
• LB and UB data byte control
• Read/write endurance
• Data retention
• Operating power supply voltage
• Low power operation
: 262,144 words × 16 bits
: Available Configuration of 524,288 words × 8 bits
: 10
13
times / 16 bits
: 10 years ( + 85 °C),
95 years ( + 55 °C), over 200 years ( + 35 °C)
: 1.8 V to 3.6 V
: Operating power supply current 20 mA (Max)
Standby current 150 μA (Max)
Sleep current 20 μA (Max)
• Operation ambient temperature range
: − 40 °C to + 85 °C
• Package
: 44-pin plastic TSOP (FPT-44P-M34)
RoHS compliant
Copyright 2013-2016 FUJITSU SEMICONDUCTOR LIMITED
2016.10
MB85R4M2T
PIN ASSIGNMENTS
(TOP VIEW)
A4
A3
A2
A1
A0
/ CE
I/ O0
I/ O1
I/ O2
I/ O3
VDD
VSS
I/ O4
I/ O5
I/ O6
I/ O7
/ WE
A17
A16
A15
A14
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
/ OE
/ UB
/ LB
I/ O15
I/ O14
I/ O13
I/ O12
VSS
VDD
I/ O11
I/ O10
I/ O9
I/ O8
/ ZZ
A8
A9
A10
A11
A12
FPT- 44P- M34
2
DS501-00024-4v0-E
MB85R4M2T
PIN DESCRIPTIONS
Pin Number
1 to 5, 18 to 22,
23 to 27, 42 to 44
Pin Name
A0 to A17
Functional Description
Address Input pins
Select 262,144 words in FRAM memory array by 18 Address
Input pins. When these address inputs are changed during /CE
equals to “L” level, reading operation of data selected in the
address after transition will start.
Data Input/Output pins
These are 16 bits bidirectional pins for reading and writing.
Chip Enable Input pin
In case the /CE equals to “L” level and /ZZ equals to “H” level,
device is activated and enables to start memory access.
In writing operation, input data from I/O pins are latched at the
rising edge of /CE and written to FRAM memory array.
Write Enable Input pin
Writing operation starts at the falling edge of /WE.
Input data from I/O pins are latched at the rising edge of /WE
and written to FRAM memory array.
Output Enable Input pin
When the /OE is “L” level, valid data are output to data bus.
When the /OE is “H” level, all I/O pins become high impedance
(High-Z) state.
Sleep Mode Input pin
When the /ZZ becomes to “L” level, device transits to the Sleep
Mode.
During reading and writing operation, /ZZ pin shall be hold “H”
level.
Lower/Upper byte Control Input pins
In case /LB or /UB equals to “L” level, it enables
reading/writing operation of I/O0 to I/O7 or I/O8 to I/O15
respectively. In case /LB and /UB equal to “H” level, all I/O
pins become High-Z state.
Supply Voltage pins
Connect all two pins to the power supply.
Ground pins
Connect all two pins to ground.
7 to 10, 13 to 16,
29 to 32, 35 to 38
6
I/O0 to I/O15
/CE
17
/WE
41
/OE
28
/ZZ
39, 40
/LB, /UB
11, 33
12, 34
VDD
VSS
Note: Please refer to the timing diagram for functional description of each pin.
DS501-00024-4v0-E
3
MB85R4M2T
BLOCK DIAGRAM
A0 to A17
Address
/ZZ
/CE
Row Decoder
FRAM Array
262,144×16
/WE
Control circuits
/OE
/UB
/LB
Column Decoder / Sense Amp.
/ Write Amp.
I/O0 to I/O15
FUNCTIONAL TRUTH TABLE
Operation Mode
Sleep
Standby
Read
Address Access Read
Write(/CE Control)
*1
Write(/WE Control)
*1*2
Address Access Write
*1*3
Pre-charge
/CE
×
H
↓
L
↓
L
L
↑
/WE
×
×
H
H
L
↓
↓
×
/OE
×
×
L
L
×
×
×
×
A0 to A17
×
×
H or L
↑ or ↓
H or L
H or L
↑ or ↓
×
/ZZ
L
H
H
H
H
H
H
H
Note: H= “H” level,
L= “L” level,
↑=
Rising edge,
↓=
Falling edge,
×= H, L,
↓
or
↑
*1: In writing cycle, input data is latched at early rising edge of /CE or /WE.
*2: In writing sequence of /WE control, there exists time with data output of reading cycle at the falling
edge of /CE.
*3: In writing sequence of Address Access Write, there exists time with data output of reading cycle at the
address transition.
4
DS501-00024-4v0-E
MB85R4M2T
State Transition Diagram
/CE=L, /ZZ=H
Power Up
Standby
/CE=H,/ZZ=H
/ZZ=H
/ZZ=L
RD/WR
Operation
Sleep
FUNCTIONAL TRUTH TABLE OF BYTE CONTROL
Operation Mode
Read(Without Output)
Read(I/O8 to I/O15)
Read(I/O0 to I/O7)
Read(I/O0 to I/O15)
Write(I/O8 to I/O15)
Write(I/O0 to I/O7)
Write(I/O0 to I/O15)
/WE
H
H
H
↑
/OE
H
×
L
/LB
×
H
H
L
L
H
L
L
/UB
×
H
L
H
L
L
H
L
I/O0 to I/O7
Hi-Z
Hi-Z
Hi-Z
Output
Output
×
Input
Input
I/O8 to I/O15
Hi-Z
Hi-Z
Output
Hi-Z
Output
Input
×
Input
×
Note: H= “H” level,
L= “L” level,
Hi-Z= High Impedance
↑= Rising edge,
↓=
Falling edge,
×= H, L,
↓
or
↑
In case the byte reading or writing are not selected, /LB and /UB pins shall be connected to GND pin.
DS501-00024-4v0-E
5
RF/Wirelessly
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