Micro-Monitor
FEATURES
• Halts and restarts an out-of-control μ-processor
• Holds μ-processor in check during power transients
• Automatically restarts μ-processor after power failure
• Monitors push-button for external override
• Accurate 5% or 10% μ-processor power supply
monitoring
• Eliminates the need for discrete components
SOP-8
DS1232
APPLICATIONS
• μ-processor Power Monitoring
• Intelligent Instruments
• Computers and Controllers
• Automotive Systems
ORDERING INFORMATION
Device
DS1232D
DS1232N
DIP-8
Package
SOP-8
DIP-8
DESCRIPTION
The DS1232 Micro-Monitor monitors three vital conditions for a microprocessor: power supply, software execution,
and external override.
First, a precision temperature compensated reference and comparator circuit monitors
the status of VCC. When an out–of–tolerance condition occurs, an internal power fail signal is generated which
forces reset to the active state. When VCC returns to an in–tolerance condition, the reset signals are kept in the
active state for a minimum of 250ms to allow the power supply and processor to stabilize.
the DS1232 performs is pushbutton reset control.
The second function
The DS1232 debounces the pushbutton input and guarantees
an active reset pulse width of 250ms minimum. The third function is a watchdog timer. The DS1232 has an
internal timer that forces the reset signals to the active state if the strobe input is not driven low prior to time–out.
The watchdog timer function can be set to operate on time–out settings of approximately 150ms, 600ms, and 1.2
seconds.
ABSOLUTE MAXIMUM RATINGS
CHARACTERISTIC
Supply Voltage
Input / Output Voltage
Operating Ambient Temperature Range
Storage Temperature
SYMBOL
V
CC
PBRST , TD, TOL, RST , RST, ST
T
A
T
STG
MIN.
-0.5
-0.5
-10
-55
MAX.
7.0
V
CC
+0.5
70
125
UNIT
V
V
°C
°C
Oct. 2019 – Rev 1.0
1/7
HTC
Micro-Monitor
RECOMMENDED OPERATIONG CONDITIONS
CHARACTERISTIC
Supply Voltage
ST and PBRST Input High Level
ST and PBRST Input Low Level
DS1232
SYMBOL
V
CC
V
IH
V
IL
MIN.
4.5
2.0
-0.3
MAX.
5.5
V
CC
+0.3
0.8
UNIT
V
V
V
ORDERING INFORMATION
Package
SOP-8
DIP-8
Order No.
DS1232D
DS1232N
Description
Micro-Monitor
Micro-Monitor
Supplied As
Reel
Tube
Status
Active
Active
Oct. 2019 – Rev 1.0
2/7
HTC
Micro-Monitor
PIN CONFIGURATION
DS1232
PBRST 1
TD 2
TOL 3
GND 4
8
7
6
5
VCC
ST
RST
RST
SOP-8 / DIP-8
PIN DESCRIPTION
Pin No.
Pin Name
SOP-8
1
2
3
4
5
6
7
8
DIP-8
1
2
3
4
5
6
7
8
PBRST
TD
TOL
GND
RST
RST
ST
V
CC
Pushbutton Reset Input
Time Delay Set
Selects 5% or 10% V
CC
Detect
Ground
Reset Output (Active High)
Reset Output (Active Low, Open Drain)
Strobe Input
5V Supply Power
Pin Function
Oct. 2019 – Rev 1.0
3/7
HTC
Micro-Monitor
ELECTRICAL CHARACTERISTICS
DS1232
Specifications with standard type face are for T
A
= 25°C, V
CC
= 5V, and those with
boldface type
are for
-10°C to 70°C
unless
(Note 1)
otherwise noted.
PARAMETER
DC ELECTRICAL CHARACTERISTICS
Input Leakage
Output Current @ 2.4V
Output Current @ 0.4V
Low Level @ RST
Output Voltage @ -500µA
Operating Current
V
CC
Trip Point
V
CC
Trip Point
AC ELECTRICAL CHARACTERISTICS
PBRST
= V
IL
RESET Active Time
ST
Pulse Width
V
CC
Fail Detect to RST and RST
V
CC
Slew Rate 4.75V to 4.25V
V
CC
Detect to RST and RST
Transition
V
CC
Slew Rate 4.25V to 4.75V
PBRST Stable Low to RST and RST
CAPACITANCE
Input Capacitance
Output Capacitance
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I
IL
I
OH
I
OL
V
OL
V
OH
I
CC
V
CCTP1
V
CCTP2
(Note 3)
-1.0
-8
8
-10
10
1.0
µA
mA
mA
(Note 5)
(Note 1)
0.4
V
CC
-0.5
V
CC
-0.1
0.5
(Note 1)
V
V
(Note 1, 7)
(Note 2)
2.0
4.74
4.49
mA
V
V
TOL=GND
TOL=V
CC
4.50
4.25
4.62
4.37
(Note 1)
t
PB
t
RST
t
ST
t
RPD
t
F
t
RPU
t
R
t
PDLY
(Note 4)
(Note 6, 8)
20
250
20
100
300
250
0
610
5
20
1000
175
610
1000
ms
ms
ns
µs
µs
ms
µs
ms
C
IN
C
OUT
5
7
pF
pF
Note 1. All voltages referenced to ground.
Note 2. Measured with outputs open.
Note 3.
½½½½½½½½½
is internally pulled up to V
CC
with an internal impedance of 10K typical.
PBRST
Note 4. t
R
= 5 μs.
½½½½½
Note 5.
RST
is an open drain output.
Note 6. Must not exceed t
TD
minimum. See Table 1.
Note 7. RST remains within 0.5V of VCC on power–down until VCC drops below 2.0V.
½½½½½
remains within 0.5V of GND on power–down until VCC drops below 2.0V.
RST
Note 8. Watchdog cannot be disabled. It must be strobed to avoid resets.
Oct. 2019 – Rev 1.0
4/7
HTC
Micro-Monitor
TYPICAL APPLICATION INFORMATION
DS1232
Fig.1. Block Diagram
Fig 2. Typical Application
Power Monitor
The DS1232 detects out-of-tolerance power supply conditions and warns a processor-based system of impending
power failure. When V
CC
falls below a preset level as defined by TOL (Pin 3), the V
CC
comparator outputs the
RST
signals RST (Pin 5) and
½½½½½
(Pin 6). When TOL is connected to ground, the RST and
½½½½½
signals become
RST
RST
active as V
CC
falls below 4.75 volts. When TOL is connected to V
CC
, the RST and
½½½½½
signals become active
½½½½½
as V
CC
falls below 4.5 volts. The RST and
RST
are excellent control signals for a microprocessor, as processing
½½½½½
is stopped at the last possible moments of valid V
CC
. On power-up, RST and
RST
are kept active for a minimum
of 250 ms to allow the power supply and processor to stabilize.
Pushbutton Reset
The DS1232 provides an input pin for direct connection to a pushbutton. The pushbutton reset input requires an
active low signal. Internally, this input is debounced and timed such that RST and
½½½½½
signals of at least 250
RST
ms minimum are generated. The 250 ms delay starts as the pushbutton reset input is released from low level.
Watchdog Timer
ST
A watchdog timer function forces RST and
½½½½½
signals to the active state when the
½½½
input is not stimulated for
RST
a predetermined time period. The time period is set by the TD input to be typically 150 ms with TD connected to
ground, 600 ms with TD left unconnected, and 1.2 seconds with TD connected to V
CC
. The watchdog timer
starts timing out from the set time period as soon as RST and
½½½½½
are inactive. If a high-to-low transition
RST
occurs on the
½½½
input pin prior to timeout, the watchdog timer is reset and begins to timeout again. If the
ST
½½½½½
watchdog timer is allowed to timeout, then the RST and
RST
signals are driven to the active state for 250 ms
minimum. The
½½½
input can be derived from microprocessor address signals, data signals, and/or control
ST
Oct. 2019 – Rev 1.0
5/7
HTC
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