查询IDT71V256供应商
LOW POWER
3.3V CMOS FAST SRAM
256K (32K x 8-BIT)
Integrated Device Technology, Inc.
IDT71V256SA
FEATURES
• Ideal for high-performance processor secondary cache
• Commercial (0° to 70°C) and Industrial (-40° to 85°C)
temperature options
• Fast access times:
— Commercial: 10/12/15/20ns
— Industrial: 15ns
• Low standby current (maximum):
— 2mA full standby
• Small packages for space-efficient layouts:
— 28-pin 300 mil SOJ
— 28-pin 300 mil plastic DIP (Commercial only)
— 28-pin TSOP Type I
• Produced with advanced high-performance CMOS
technology
• Inputs and outputs are LVTTL-compatible
• Single 3.3V(±0.3V) power supply
DESCRIPTION
The IDT71V256SA is a 262,144-bit high-speed static RAM
organized as 32K x 8. It is fabricated using IDT’s high-
performance, high-reliability CMOS technology.
The IDT71V256SA has outstanding low power character-
istics while at the same time maintaining very high perfor-
mance. Address access times of as fast as10 ns are ideal for
3.3V secondary cache in 3.3V desktop designs.
When power management logic puts the IDT71V256SA in
standby mode, its very low power characteristics contribute to
extended battery life. By taking
CS
HIGH, the SRAM will
automatically go to a low power standby mode and will remain
in standby as long as
CS
remains HIGH. Furthermore, under
full standby mode (
CS
at CMOS level, f=0), power consump-
tion is guaranteed to always be less than 6.6mW and typically
will be much smaller.
The IDT71V256SA is packaged in 28-pin 300 mil SOJ, 28-
pin 300 mil plastic DIP, and 28-pin 300 mil TSOP Type I
packaging.
FUNCTIONAL BLOCK DIAGRAM
A
0
ADDRESS
DECODER
A
14
262,144 BIT
MEMORY ARRAY
V
CC
GND
I/O
0
INPUT
DATA
CIRCUIT
I/O
7
I/O CONTROL
CS
OE
WE
CONTROL
CIRCUIT
3101 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
©1997
Integrated Device Technology, Inc.
MAY 1997
DSC-3101/04
1
IDT71V256SA
3.3V CMOS STATIC RAM 256K (32K x 8-BIT)
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
ABSOLUTE MAXIMUM RATINGS
(1)
V
CC
WE
Symbol
V
CC
V
TERM(2)
T
BIAS
T
STG
P
T
I
OUT
Rating
Supply Voltage
Relative to GND
Terminal Voltage
Relative to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
–0.5 to +4.6
–0.5 to V
CC
+0.5
–55 to +125
–55 to +125
1.0
50
Unit
V
V
°C
°C
W
mA
A
13
A
8
A
9
A
11
OE
SO28-5
P28-2
22
21
20
19
18
17
16
15
A
10
CS
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
3101 drw 02
DIP/SOJ
TOP VIEW
OE
NOTES:
3101 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Input, Output, and I/O terminals; 4.6V maximum.
A
10
CS
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
A
11
A
9
A
8
A
13
WE
V
CC
A
14
A
12
A
7
A
6
A
5
A
4
A
3
SO28-8
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
3101 drw 11
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz, SOJ package)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max. Unit
6
7
pF
pF
TSOP
TOP VIEW
NOTE:
3101 tbl 04
1. This parameter is determined by device characterization, but is not
production tested.
PIN DESCRIPTIONS
Name
A
0
–A
14
I/O
0
–I/O
7
CS
WE
OE
Description
Addresses
Data Input/Output
Chip Select
Write Enable
Output Enable
Ground
Power
3101 tbl 01
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Commercial
Industrial
Temperature
0°C to +70°C
-40°C to +85°C
GND
0V
0V
V
CC
3.3V
±
0.3V
3.3V
±
0.3V
3101 tbl 05
GND
V
CC
TRUTH TABLE
(1)
WE
CS
OE
I/O
High-Z
High-Z
High-Z
D
OUT
D
IN
Function
Standby (ISB)
Standby (ISB1)
Output Disable
Read
Write
3101 tbl 02
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
V
CC
GND
V
IH
V
IH
V
IL
Parameter
Supply Voltage
Supply Voltage
Input High Voltage - Inputs
Input High Voltage - I/O
Input Low Voltage
Min. Typ.
3.0
0
2.0
2.0
–0.3
(1)
3.3
0
—
—
—
Max. Unit
3.6
0
5.0
Vcc+0.3
X
X
H
H
L
H
V
HC
L
L
L
X
X
H
L
X
V
V
V
V
V
NOTE:
1. H = V
IH
, L = V
IL
, X = Don’t Care
0.8
NOTE:
3101 tbl 06
1. V
IL
(min.) = –2.0V for pulse width less than 5ns, once per cycle.
2
IDT71V256SA
3.3V CMOS STATIC RAM 256K (32K x 8-BIT)
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(1, 2)
(V
CC
= 3.3V
±
0.3V, V
LC
= 0.2V, V
HC
= V
CC
- 0.2V)
Symbol
I
CC
I
SB
I
SB1
Parameter
Dynamic Operating Current
CS
≤
V
IL
, Outputs
Open, V
CC
= Max., f = f
MAX(2)
Standby Power Supply Current (TTL Level)
(2)
CS
= V
IH
, V
CC
= Max., Outputs Open, f = f
MAX
Full Standby Power Supply Current (CMOS Level)
(2)
CS
≥
V
HC
, V
CC
= Max., Outputs Open, f = 0
,
V
IN
≤
V
LC
or V
IN
≥
V
HC
71V256SA10
(3)
71V256SA12
(3)
71V256SA15 71V256SA20
(3)
Unit
100
20
2
90
20
2
85
20
2
85
20
2
mA
mA
mA
NOTES:
1. All values are maximum guaranteed values.
2. f
MAX
= 1/t
RC
, only address inputs cycling at fmax; f = 0 means that no inputs are cycling.
3. Commercial temperature range only.
3101 tbl 07
DC ELECTRICAL CHARACTERISTICS
V
CC
= 3.3V± 0.3V
IDT71V256SA
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Condition
V
CC
= Max., V
IN
= GND to V
CC
V
CC
= Max.,
CS
= V
IH,
V
OUT
= GND to V
CC
I
OL
= 8mA, V
CC
= Min.
I
OH
= –4mA, V
CC
= Min.
Min.
—
—
—
2.4
Typ.
—
—
—
—
Max.
2
2
0.4
—
Unit
µA
µA
V
V
3101 tbl 08
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
3ns
1.5V
1.5V
See Figures 1 and 2
3101 tbl 09
3.3V
320
Ω
DATA
OUT
350
Ω
30pF*
3.3V
320Ω
DATA
OUT
350Ω
5pF*
3101 drw 04
3101 drw 05
Figure 1. AC Test Load
Figure 2. AC Test Load
(for t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
OW
, t
WHZ
)
*Includes scope and jig capacitances
3
IDT71V256SA
3.3V CMOS STATIC RAM 256K (32K x 8-BIT)
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 3.3V
±
0.3V)
71V256SA10
(2)
Symbol
Parameter
Max.
10
—
—
5
0
—
3
2
3
10
9
9
0
9
0
6
0
4
1
Min.
—
10
10
—
8
6
—
6
—
—
—
—
—
—
—
—
—
—
8
Read Cycle
t
RC
Read Cycle Time
t
AA
Address Access Time
t
ACS
t
CLZ(1)
t
CHZ(1)
t
OE
t
OLZ
t
OHZ(1)
t
OH
(1)
71V256SA12
(2)
Min.
12
—
—
5
0
—
3
2
3
12
9
9
0
9
0
6
0
4
1
Max.
—
12
12
—
8
6
—
6
—
—
—
—
—
—
—
—
—
—
8
71V256SA15
Min.
15
—
—
5
0
—
0
0
3
15
10
10
0
10
0
7
0
4
1
Max.
—
15
15
—
9
7
—
7
—
—
—
—
—
—
—
—
—
—
9
71V256SA20
(2)
Min.
20
—
—
5
0
—
0
0
3
20
15
15
0
15
0
8
0
4
1
Max.
—
20
20
—
10
8
—
8
—
—
—
—
—
—
—
—
—
—
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3101 tbl 10
Chip Select Access Time
Chip Select to Output in Low-Z
Chip Select to Output in High-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
Output Hold from Address Change
Write Cycle
t
WC
Write Cycle Time
t
AW
Address Valid to End-of-Write
t
CW
Chip Select to End-of-Write
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW(1)
t
WHZ(1)
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End-of-Write
Write Enable to Output in High-Z
NOTE:
1. This parameter guaranteed with the AC test load (Figure 2) by device characterization, but is not production tested.
2. Commercial temperature range only.
TIMING WAVEFORM OF READ CYCLE NO. 1
(1)
t
RC
ADDRESS
t
AA
OE
t
OH
t
OE
t
OLZ
CS
(2)
t
OHZ
(2)
t
ACS
t
CLZ
DATA
OUT
(2)
t
CHZ
DATA VALID
(2)
3101 drw 06
NOTES:
1.
WE
is HIGH for Read cycle.
2. Transition is measured
±200mV
from steady state.
4
IDT71V256SA
3.3V CMOS STATIC RAM 256K (32K x 8-BIT)
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 2
(1, 2, 4)
t
RC
ADDRESS
t
AA
t
OH
DATA
OUT
PREVIOUS DATA VALID
DATA VALID
3101 drw 07
t
OH
TIMING WAVEFORM OF READ CYCLE NO. 3
(1, 3, 4)
CS
t
ACS
t
CLZ (5)
DATA
OUT
DATA VALID
t
CHZ
(5)
3101 drw 08
NOTES:
1.
WE
is HIGH for Read cycle.
2. Device is continuously selected,
CS
is LOW.
3. Address valid prior to or coincident with
CS
transition LOW.
4.
OE
is LOW.
5. Transition is measured
±200mV
from steady state.
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
WE
CONTROLLED TIMING)
(1, 2, 3, 5, 7)
t
WC
ADDRESS
t
OHZ
OE
(6)
t
AW
CS
t
AS
WE
t
WP
(7)
t
WR
t
WHZ
DATA
OUT
(4)
(6)
t
OW (6)
(4)
t
DW
DATA
IN
t
DH
DATA VALID
3101 drw 09
NOTES:
1.
WE
or
CS
must be HIGH during all address transitions.
2. A write occurs during the overlap of a LOW
CS
and a LOW
WE
.
3. t
WR
is measured from the earlier of
CS
or
WE
going HIGH to the end of the write cycle.
4. During this period, I/O pins are in the output state so that the input signals must not be applied.
5. If the
CS
LOW transition occurs simultaneously with or after the
WE
LOW transition, the outputs remain in a high-impedance state.
6. Transition is measured
±200mV
from steady state.
7. If
OE
is LOW during a
WE
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WHZ
+ t
DW
) to allow the I/O drivers to turn off and data
to be placed on the bus for the required t
DW
. If
OE
is HIGH during a
WE
controlled write cycle, this requirement does not apply and the write pulse can
be as short as the spectified t
WP.
5
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