Data Sheet No. PD60262
IRS2181/IRS21814(S)PbF
Features
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HIGH AND LOW SIDE DRIVER
Packages
8-Lead PDIP
IRS2181
14-Lead PDIP
IRS21814
Floating channel designed for bootstrap operation
Fully operational to +600 V
Tolerant to negative transient voltage, dV/dt
immune
Gate drive supply range from 10 V to 20 V
Undervoltage lockout for both channels
3.3 V and 5 V input logic compatible
Matched propagation delay for both channels
Logic and power ground +/- 5 V offset
Lower di/dt gate driver for better noise immunity
Output source/sink current capability 1.4 A/1.8 A
RoHS compliant
8-Lead SOIC
IRS2181S
14-Lead SOIC
IRS21814S
Description
Feature Comparison
Cross-
The IRS2181/IRS21814 are high
ton/toff
Deadtime
Input
conduction
Ground Pins
Part
voltage, high speed power MOSFET
(ns)
(ns)
logic
prevention
logic
and IGBT drivers with independent
2181
COM
HIN/LIN
no
none
180/220
high-side and low-side referenced
21814
V
SS
/COM
output channels. Proprietary HVIC
2183
Internal 400
COM
HIN/LIN
yes
180/220
21834
Program 400-5000
V
SS/
COM
and latch immune CMOS technolo-
2184
Internal 400
COM
IN/SD
yes
680/270
gies enable ruggedized monolithic
21844
Program 400-5000
V
SS
/COM
construction. The logic input is com-
patible with standard CMOS or LSTTL output, down to 3.3 V logic. The output drivers feature a high pulse
current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive
an N-channel power MOSFET or IGBT in the high-side configuration which operates up to 600 V.
Typical Connection
up to 600 V
V
CC
V
CC
HIN
LIN
V
B
HO
V
S
LO
TO
LOAD
HIN
LIN
COM
IRS2181
IRS21814
HO
V
CC
HIN
LIN
up to 600 V
V
CC
HIN
LIN
V
B
V
S
TO
LOAD
(Refer to Lead Assignments for correct pin
configuration). These diagrams show
electrical connections only. Please refer to
our Application Notes and DesignTips for
proper circuit board layout.
V
SS
V
SS
COM
LO
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1
IRS2181/IRS21814(S)PbF
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions.
Symbol
V
B
V
S
V
HO
V
CC
V
LO
V
IN
V
SS
dV
S
/dt
Definition
High-side floating absolute voltage
High-side floating supply offset voltage
High-side floating output voltage
Low-side and logic fixed supply voltage
Low-side output voltage
Logic input voltage (HIN & LIN)
Logic ground (IRS21814 only)
Allowable offset supply voltage transient
(8-lead PDIP)
Min.
-0.3
V
B
- 20
V
S
- 0.3
-0.3
-0.3
V
SS
- 0.3
V
CC
- 20
—
—
—
—
—
—
—
—
—
—
-50
—
Max.
620
(Note 1)
V
B
+ 0.3
V
B
+ 0.3
20
(Note 1)
V
CC
+ 0.3
V
CC
+ 0.3
V
CC
+ 0.3
50
1.0
0.625
1.6
1.0
125
200
75
120
150
150
300
Units
V
V/ns
P
D
Package power dissipation @ T
A
≤
+25 °C
(8-lead SOIC)
(14-lead PDIP)
(14-lead SOIC)
(8-lead PDIP)
(8-lead SOIC)
(14-lead PDIP)
(14-lead SOIC)
W
Rth
JA
Thermal resistance, junction to ambient
°C/W
T
J
T
S
T
L
Junction temperature
Storage temperature
Lead temperature (soldering, 10 seconds)
°C
Note 1: All supplies are fully tested at 25 V and an internal 20 V clamp exists for each supply.
Recommended Operating Conditions
The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the
recommended conditions. The V
S
and V
SS
offset rating are tested with all supplies biased at a 15 V differential.
Symbol
VB
V
S
V
HO
V
CC
V
LO
V
IN
V
SS
T
A
Definition
High-side floating supply absolute voltage
High-side floating supply offset voltage
High-side floating output voltage
Low-side and logic fixed supply voltage
Low-side output voltage
Logic input voltage (HIN & LIN)
Logic ground (IRS21814 only)
Ambient temperature
Min.
V
S
+ 10
Note 2
V
S
10
0
V
SS
-5
-40
Max.
V
S
+ 20
600
V
B
20
V
CC
V
CC
5
125
Units
V
°C
Note 2: Logic operational for V
S
of -5 V to +600 V. Logic state held for V
S
of -5 V to -V
BS
. (Please refer to the Design Tip
DT97-3 for more details).
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2
IRS2181/IRS21814(S)PbF
Dynamic Electrical Characteristics
V
BIAS
(V
CC
, V
BS
) = 15 V, V
SS
= COM, C
L
= 1000 pF, T
A
= 25
°C.
Symbol
ton
toff
MT
tr
tf
Definition
Turn-on propagation delay
Turn-off propagation delay
Delay matching, HS & LS turn-on/off
Turn-on rise time
Turn-off fall time
Min.
—
—
—
—
—
Typ.
180
220
0
40
20
Max. Units Test Conditions
270
330
35
60
35
ns
V
S
= 0 V
V
S
= 0 V
V
S
= 0 V or 600 V
Static Electrical Characteristics
V
BIAS
(V
CC
, V
BS
) = 15 V, V
SS
= COM and T
A
= 25
°C
unless otherwise specified. The V
IL
, V
IH,
and I
IN
parameters are
referenced to V
SS
/COM and are applicable to the respective input leads HIN and LIN. The V
O
, I
O,
and Ron parameters
are referenced to COM and are applicable to the respective output leads: HO and LO.
Symbol
V
IH
V
IL
V
OH
V
OL
I
LK
I
QBS
I
QCC
I
IN+
I
IN-
V
CCUV+
V
BSUV+
V
CCUV-
V
BSUV-
V
CCUVH
V
BSUVH
I
O+
I
O-
Definition
Logic “1” input voltage
Logic “0” input voltage
High level output voltage, V
BIAS
- V
O
Low level output voltage, V
O
Offset supply leakage current
Quiescent V
BS
supply current
Quiescent V
CC
supply current
Logic “1” input bias current
Logic “0” input bias current
V
CC
and V
BS
supply undervoltage positive going
threshold
V
CC
and V
BS
supply undervoltage negative going
threshold
Hysteresis
Output high short circuit pulsed current
Output low short circuit pulsed current
Min. Typ. Max. Units Test Conditions
2.5
—
—
—
—
20
50
—
—
8.0
7.4
0.3
1.4
1.8
—
—
—
—
—
60
120
25
—
8.9
8.2
0.7
1.9
2.3
—
0.8
1.4
0.2
50
150
240
60
5.0
9.8
V
9.0
—
—
A
—
V
O
= 0 V,
PW
≤
10
µs
V
O
= 15 V,
PW
≤
10
µs
µA
V
I
O
= 0 A
I
O
= 20 mA
V
B
= V
S
= 600 V
V
IN
= 0 V or 5 V
V
IN
= 5 V
V
IN
= 0 V
V
CC
= 10 V to 20 V
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IRS2181/IRS21814(S)PbF
Functional Block Diagrams
VB
2181
HIN
VSS/COM
LEVEL
SHIFT
HV
LEVEL
SHIFTER
PULSE
GENERATOR
UV
DETECT
R
PULSE
FILTER
R
S
Q
HO
VS
VCC
UV
DETECT
LO
LIN
VSS/COM
LEVEL
SHIFT
DELAY
COM
VB
21814
HIN
VSS/COM
LEVEL
SHIFT
HV
LEVEL
SHIFTER
PULSE
GENERATOR
UV
DETECT
R
PULSE
FILTER
R
S
Q
HO
VS
VCC
UV
DETECT
LO
LIN
VSS/COM
LEVEL
SHIFT
DELAY
COM
VSS
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IRS2181/IRS21814(S)PbF
Lead Definitions
Symbol Description
HIN
LIN
VSS
V
B
HO
V
S
V
CC
LO
COM
Logic input for high-side gate driver output (HO), in phase (IRS2181/IRS21814)
Logic input for low-side gate driver output (LO), in phase (IRS2181/IRS21814)
Logic ground (IRS21814 only)
High-side floating supply
High-side gate drive output
High-side floating supply return
Low-side and logic fixed supply
Low-side gate drive output
Low-side return
Lead Assignments
1
2
3
4
HIN
LIN
COM
LO
VB
HO
VS
VCC
8
7
6
5
1
2
3
4
HIN
LIN
COM
LO
VB
HO
VS
VCC
8
7
6
5
8-Lead PDIP
8-Lead SOIC
IRS2181PbF
IRS2181SPbF
1
2
3
4
5
6
7
HIN
LIN
VSS
VB
HO
VS
COM
LO
VCC
1
4
13
1
2
3
HIN
LIN
VSS
VB
HO
VS
COM
LO
VCC
1
4
13
12
11
10
9
8
12
4
11
5
10
6
9
7
8
14-Lead PDIP
14-Lead SOIC
IRS21814PbF
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IRS21814SPbF
5
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