19-3558; Rev 4; 8/09
KIT
ATION
EVALU
BLE
AVAILA
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
General Description
Features
♦
Proprietary Data Encoding for DC Balance and
Reduced EMI
♦
Control Data Sent During Video Blanking
♦
Five Control Data Inputs Are Single-Bit-Error
Tolerant
♦
Output Common-Mode Filter Reduces EMI
♦
Greater than 10m STP Cable Drive
♦
Wide ±2% Reference Clock Tolerance
♦
ISO 10605 ESD Protection
♦
Separate Input Supply Allows Interface to 1.8V to
3.3V Logic
♦
+3.3V Core Supply
♦
Space-Saving Thin QFN and LQFP Packages
♦
-40°C to +85°C Operating Temperature
MAX9217
The MAX9217 digital video parallel-to-serial converter
serializes 27 bits of parallel data into a serial data stream.
Eighteen bits of video data and 9 bits of control data are
encoded and multiplexed onto the serial interface, reduc-
ing the serial data rate. The data enable input determines
when the video or control data is serialized.
The MAX9217 pairs with the MAX9218 deserializer to
form a complete digital video serial link. Interconnect
can be controlled-impedance PCB traces or twisted-pair
cable. Proprietary data encoding reduces EMI and pro-
vides DC balance. DC balance allows AC-coupling,
providing isolation between the transmitting and receiv-
ing ends of the interface. The LVDS output is internally
terminated with 100Ω.
ESD tolerance is specified for ISO 10605 with ±10kV
contact discharge and ±30kV air discharge.
The MAX9217 operates from a +3.3V core supply and
features a separate input supply for interfacing to 1.8V
to 3.3V logic levels. This device is available in 48-lead
Thin QFN and LQFP packages and is specified from
-40°C to +85°C.
Ordering Information
PART
MAX9217ECM+
MAX9217ECM/V+
MAX9217ETM+
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-
PACKAGE
48 LQFP
48 LQFP
48 Thin QFN-EP*
Applications
Navigation System Display
In-Vehicle Entertainment System
Video Camera
LCD Displays
OUT-
LVDS GND
LVDS GND
CMF
PWRDWN
V
CCPLL
PLL GND
I.C.
+Denotes
a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
*EP
= Exposed pad.
Pin Configurations
RNG1
V
CCLVDS
RNG0
RNG1
V
CCLVDS
OUT+
OUT-
LVDS GND
LVDS GND
CMF
PWRDWN
V
CCPLL
36
35
34
33
32
31
30
29
28
27
24
23
22
21
20
19
RNG0
OUT+
TOP VIEW
36
35
34
33
32
31
30
29
28
27
26
25
26
GND
V
CC
RGB_IN0
RGB_IN1
RGB_IN2
RGB_IN3
RGB_IN4
RGB_IN5
RGB_IN6
RGB_IN7
RGB_IN8
RGB_IN9
37
38
39
40
41
42
43
44
45
46
47
48
MAX9217
18
17
16
15
14
13
+
1
2
3
4
5
6
7
8
9
10
11
12
I.C.
PCLK_IN
DE_IN
CNTL_IN8
CNTL_IN7
CNTL_IN6
CNTL_IN5
CNTL_IN4
CNTL_IN3
CNTL_IN2
V
CC
GND
25
PLL GND
I.C.
GND
V
CC
RGB_IN0
RGB_IN1
RGB_IN2
RGB_IN3
RGB_IN4
RGB_IN5
RGB_IN6
RGB_IN7
RGB_IN8
RGB_IN9
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
I.C
PCLK_IN
DE_IN
CNTL_IN8
CNTL_IN7
CNTL_IN6
CNTL_IN5
CNTL_IN4
CNTL_IN3
CNTL_IN2
V
CC
GND
MAX9217
18
17
16
15
14
13
+
1
2
3
4
5
6
7
8
9
10
11
12
GND
V
CCIN
RGB_IN10
RGB_IN11
RGB_IN12
RGB_IN13
RGB_IN14
RGB_IN15
RGB_IN16
RGB_IN17
CNTL_IN0
CNTL_IN1
LQFP
________________________________________________________________
Maxim Integrated Products
GND
V
CCIN
RGB_IN10
RGB_IN11
RGB_IN12
RGB_IN13
RGB_IN14
RGB_IN15
RGB_IN16
RGB_IN17
CNTL_IN0
CNTL_IN1
THIN QFN-EP
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
MAX9217
ABSOLUTE MAXIMUM RATINGS
V
CC_
to _GND........................................................-0.5V to +4.0V
Any Ground to Any Ground...................................-0.5V to +0.5V
OUT+, OUT- to LVDS GND ...................................-0.5V to +4.0V
OUT+, OUT- Short Circuit to LVDS GND
or V
CCLVDS
.............................................................Continuous
OUT+, OUT- Short Through 0.125µF (or smaller),
25V Series Capacitor..........................................-0.5V to +16V
RGB_IN[17:0], CNTL_IN[8:0], DE_IN,
RNG0, RNG1, PCLK_IN,
PWRDWN,
CMF to GND......................-0.5V to (V
CCIN
+ 0.5V)
Continuous Power Dissipation (T
A
= +70°C)
48-Lead LQFP (derate 21.7mW/°C above +70°C) ....1739mW
48-Lead Thin QFN (derate 37mW/°C above +70°C) .2963mW
ESD Protection
Machine Model (R
D
= 0Ω, CS = 200pF)
All Pins to GND ..............................................................±200V
Human Body Model (R
D
= 1.5kΩ, CS = 100pF)
All Pins to GND ................................................................±2kV
ISO 10605 (R
D
= 2kΩ, C
S
= 330pF)
Contact Discharge (OUT+, OUT-) to GND ....................±10kV
Air Discharge (OUT+, OUT-) to GND ............................±30kV
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature ......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC_
= +3.0V to +3.6V, R
L
= 100Ω ±1%,
PWRDWN
= high, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at
V
CC_
= +3.3V, T
A
= +25°C.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS
V
CCIN
= 1.71V to <3V
V
CCIN
= 1.71V to <3V
V
IN
= -0.3V to (V
CCIN
+ 0.3V),
V
CCIN
= 1.71V to 3.6V,
PWRDWN
= high or low
I
CL
= -18mA
Figure 1
Figure 1
Figure 1
Figure 1
V
OUT+
or V
OUT-
= 0 or 3.6V
V
OD
= 0
PWRDWN
= low
or
V
CC_
= 0
V
OUT+
= 0,
V
OUT-
= 3.6V
V
OUT+
= 3.6V,
V
OUT-
= 0
-15
±8
5.5
1.125
1.29
250
335
MIN
0.65V
CCIN
2
-0.3
-0.3
-70
TYP
MAX
V
CCIN
+ 0.3
V
CCIN
+ 0.3
0.3V
CCIN
+0.8
+70
-1.5
450
20
1.375
20
+15
15
UNITS
SINGLE-ENDED INPUTS (RGB_IN[17:0], CNTL_IN[8:0], DE_IN, PCLK_IN,
PWRDWN,
RNG_)
High-Level Input Voltage
Low-Level Input Voltage
V
IH
V
IL
V
V
Input Current
Input Clamp Voltage
LVDS OUTPUTS (OUT+, OUT-)
Differential Output Voltage
Change in V
OD
Between
Complementary Output States
Common-Mode Voltage
Change in V
OS
Between
Complementary Output States
Output Short-Circuit Current
Magnitude of Differential Output
Short-Circuit Current
I
IN
V
CL
V
OD
ΔV
OD
V
OS
ΔV
OS
I
OS
I
OSD
µA
V
mV
mV
V
mV
mA
mA
Output High-Impedance Current
I
OZ
-1
+1
µA
2
_______________________________________________________________________________________
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
DC ELECTRICAL CHARACTERISTICS (continued)
(V
CC_
= +3.0V to +3.6V, R
L
= 100Ω ±1%,
PWRDWN
= high, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at
V
CC_
= +3.3V, T
A
= +25°C.) (Notes 1, 2)
PARAMETER
Differential Output Resistance
SYMBOL
R
O
R
L
= 100Ω
±
1%,
C
L
= 5pF,
continuous 10
transition words,
modulation off
(Note 3)
3MHz
5MHz
10MHz
20MHz
35MHz
CONDITIONS
MIN
78
TYP
110
15
18
23
33
50
MAX
147
25
25
28
39
70
50
µA
mA
UNITS
Ω
MAX9217
Worst-Case Supply Current
I
CCW
Power-Down Supply Current
I
CCZ
AC ELECTRICAL CHARACTERISTICS
(V
CC_
= +3.0V to +3.6V, R
L
= 100Ω ±1%, C
L
= 5pF,
PWRDWN
= high, T
A
= -40°C to +85°C, unless otherwise noted. Typical values
are at V
CC_
= +3.3V, T
A
= +25°C.) (Note 4)
PARAMETER
PCLK_IN TIMING REQUIREMENTS
Clock Period
Clock Frequency
Clock Frequency Difference from
Deserializer Reference Clock
Clock Duty Cycle
Clock Transition Time
SWITCHING CHARACTERISTICS
Output Rise Time
Output Fall Time
Input Setup Time
Input Hold Time
Serializer Delay
PLL Lock Time
Power-Down Delay
t
RISE
t
FALL
t
SET
t
HOLD
t
SD
t
LOCK
t
PD
20% to 80%, V
OD
≥
250mV,
modulation off, Figure 3
80% to 20%, V
OD
≥
250mV,
modulation off, Figure 3
Figure 4
Figure 4
Figure 5
Figure 6
Figure 7
3
3
3.15 x
t
T
3.2 x
t
T
16385 x
t
T
1
215
206
350
350
ps
ps
ns
ns
ns
ns
µs
t
T
f
CLK
Δf
CLK
DC
t
R
, t
F
t
HIGH
/t
T
or t
LOW
/t
T,
Figure 2
Figure 2
Figure 2
28.57
3
-2
35
50
333.00
35
+2
65
2.5
ns
MHz
%
%
ns
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
_______________________________________________________________________________________
3
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
MAX9217
AC ELECTRICAL CHARACTERISTICS (continued)
(V
CC_
= +3.0V to +3.6V, R
L
= 100Ω ±1%, C
L
= 5pF,
PWRDWN
= high, T
A
= -40°C to +85°C, unless otherwise noted. Typical values
are at V
CC_
= +3.3V, T
A
= +25°C.) (Note 4)
PARAMETER
Peak-to-Peak Output Offset
Voltage
SYMBOL
CONDITIONS
700Mbps data rate,
CMF open, Figure 8
V
OSp-p
700Mbps data rate,
CMF 0.1µF to ground, Figure 8
MIN
TYP
22
12
MAX
70
mV
50
UNITS
Note 1:
Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except V
OD
,
ΔV
OD
, and
ΔV
OS
.
Note 2:
Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at T
A
= +25°C.
Note 3:
All LVTTL/LVCMOS inputs, except
PWRDWN
at
≤
0.3V or
≥
V
CCIN
- 0.3V.
PWRDWN
is
≤
0.3V.
Note 4:
AC parameters are guaranteed by design and characterization and are not production tested. Limits are set at ±6 sigma.
Typical Operating Characteristics
(T
A
= +25°C, V
CC_
= +3.3V, R
L
= 100Ω, modulation off, unless otherwise noted.)
WORST-CASE PATTERN
SUPPLY CURRENT vs. FREQUENCY
MAX9217 toc01
60
50
SUPPLY CURRENT (mA)
40
30
20
10
0
3
7
11
15
19
23
27
31
35
FREQUENCY (MHz)
4
_______________________________________________________________________________________
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
Pin Description
PIN
1, 13, 37
2
3–10,
39–48
11, 12, 15–21
14, 38
NAME
GND
V
CCIN
FUNCTION
Input Buffer Supply and Digital Supply Ground
Input Buffer Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible, with the smallest value capacitor closest to the supply pin.
LVTTL/LVCMOS Red, Green, and Blue Digital Video Data Inputs. Eighteen data bits are loaded
into the input latch on the rising edge of PCLK_IN when DE_IN is high. Internally pulled down to
GND.
LVTTL/LVCMOS Control Data Inputs. Control data are latched on the rising edge of PCLK_IN
when DE_IN is low. Internally pulled down to GND.
Digital Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as close to
the device as possible, with the smallest value capacitor closest to the supply pin.
LVTTL/LVCMOS Data Enable Input. Logic-high selects RGB_IN[17:0] to be latched. Logic-low
selects CNTL_IN[8:0] to be latched. DE_IN must be switching for proper operation. Internally
pulled down to GND.
LVTTL/LVCMOS Parallel Clock Input. Latches data and control inputs and provides the PLL
reference clock. Internally pulled down to GND.
Internally connected to GND. Connect to GND or leave unconnected.
PLL Supply Ground
PLL Supply Voltage. Bypass to PLL GND with 0.1µF and 0.001µF capacitors in parallel as close
to the device as possible, with the smallest value capacitor closest to the supply pin.
LVTTL/LVCMOS Power-Down Input. Internally pulled down to GND.
Common-Mode Filter. Optionally connect a capacitor between CMF and ground to filter
common-mode switching noise.
LVDS Supply Ground
Inverting LVDS Serial Data Output
Noninverting LVDS Serial Data Output
LVDS Supply Voltage. Bypass to LVDS GND with 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible, with the smallest value capacitor closest to the supply pin.
LVTTL/LVCMOS Frequency Range Select Input. Set to the frequency range that includes the
PCLK_IN frequency as shown in Table 3. Internally pulled down to GND.
LVTTL/LVCMOS Frequency Range Select Input. Set to the frequency range that includes the
PCLK_IN frequency as shown in Table 3. Internally pulled down to GND.
Exposed Pad (Thin QFN Package Only). Connect Thin QFN exposed pad to PCB GND.
MAX9217
RGB_IN[17:0]
CNTL_IN[8:0]
V
CC
22
DE_IN
23
24, 25
26
27
28
29
30, 31
32
33
34
35
36
—
PCLK_IN
I.C.
PLL GND
V
CCPLL
PWRDWN
CMF
LVDS GND
OUT-
OUT+
V
CCLVDS
RNG1
RNG0
EP
_______________________________________________________________________________________
5
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