PIC18F46J50 FAMILY
PIC18F46J50 Family
Silicon Errata and Data Sheet Clarification
The PIC18F46J50 family devices that you have received
conform functionally to the current Device Data Sheet
(DS39931C), except for the anomalies described in this
document.
The silicon issues discussed in the following pages are
for silicon revisions with the Device and Revision IDs
listed in Table 1. The silicon issues are summarized in
Table 2.
The errata described in this document will be addressed
in future revisions of the PIC18F46J50 family silicon.
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated in the last column of
Table 2 apply to the current silicon revision
(Rev. A4).
For example, to identify the silicon revision level using
MPLAB IDE in conjunction with MPLAB ICD 2 or
PICkit™ 3:
1.
Using the appropriate interface, connect the
device to the MPLAB ICD 2 programmer/
debugger or PICkit™ 3.
From the main menu in MPLAB IDE, select
Configure>Select Device,
and then select the
target part number in the dialog box.
Select
the
MPLAB
hardware
tool
(Debugger>Select
Tool).
Perform a “Connect” operation to the device
(Debugger>Connect). Depending on the devel-
opment tool used, the part number
and
Device
Revision ID value appear in the
Output
window.
Note:
If you are unable to extract the silicon
revision level, please contact your local
Microchip sales office for assistance.
2.
3.
4.
Data Sheet clarifications and corrections start on page 8,
following the discussion of silicon issues.
The silicon revision level can be identified using the
current version of MPLAB
®
IDE and Microchip’s
programmers, debuggers, and emulation tools, which
are available at the Microchip corporate web site
(www.microchip.com).
The DEVREV values for the various PIC18F46J50 family
silicon revisions are shown in Table 1.
TABLE 1:
SILICON DEVREV VALUES
Device ID
(1)
Part Number
Revision ID for Silicon Revision
(2)
A2
A4
PIC18F24J50
4C0Xh
PIC18F25J50
4C2Xh
PIC18F26J50
4C4Xh
PIC18F44J50
4C6Xh
PIC18F45J50
4C8Xh
PIC18F46J50
4CAXh
2h
4h
PIC18LF24J50
4CCXh
PIC18LF25J50
4CEXh
PIC18LF26J50
4D0Xh
PIC18LF44J50
4D2Xh
PIC18LF45J50
4D4Xh
PIC18LF46J50
4D6Xh
Note 1:
The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses of configuration
memory space. They are shown in hexadecimal in the format “DEVID DEVREV”.
2:
Refer to the
“PIC18F2XJXX/4XJXX Family Flash Microcontroller Programming Specification”
(DS39687)
for detailed information on Device and Revision IDs for your specific device.
2010 Microchip Technology Inc.
DS80436C-page 1
PIC18F46J50 FAMILY
TABLE 2:
Module
MSSP
MSSP
SILICON ISSUE SUMMARY
Feature
I
2
C™
Modes
I
2
C Slave
Item
Number
1.
2.
Issue Summary
Must keep LATB<5:4> bits clear.
Module may not receive the correct data if there
is a delay in reading SSPxBUF after SSPxIF
interrupt.
If interrupts are enabled, a 2 T
CY
delay needed
after re-enabling the module.
F
OSC
/2 A/D Conversion mode may not meet
linearity error limits.
Incorrect data capture in Slave modes.
Wake-up events that occur during Deep Sleep
entry may not generate an event.
Minimum operating voltage (V
DD
) parameter for
“F” devices is 2.25V.
At high V
DD
voltages, performing an A/D
conversion on Channel 15 could have issues.
Low voltages turn off constant current source.
Affected
Revisions
(1)
A2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A4
EUSART
A/D
PMP
Low-Power
modes
DC
Characteristics
A/D
CTMU
Note 1:
Enable/Dis-
able
F
OSC
/2
Clock
PSP
Deep Sleep
Supply Volt-
age
Band Gap
Reference
Constant
Current
3.
4.
5.
6.
7.
8.
9.
Only those issues indicated in the last column apply to the current silicon revision.
DS80436C-page 2
2010 Microchip Technology Inc.
PIC18F46J50 FAMILY
Silicon Errata Issues
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (Rev. A4).
2. Module: Master Synchronous Serial Port
(MSSP)
In extremely rare cases, when configured for I
2
C™
slave reception, the MSSP module may not receive
the correct data. This occurs only if the Serial
Receive/Transmit Buffer Register (SSPxBUF) is not
read within a window after the SSPxIF interrupt
has occurred.
Work around
The issue can be resolved in either of these ways:
• Prior to the I
2
C slave reception, enable the
clock stretching feature.
This is done by
(SSPxCON2<0>).
setting
the
SEN
bit
1. Module: Master Synchronous Serial Port
(MSSP1)
If the LATB<5> or LATB<4> bit is set, the
MSSP1 module will not work correctly in the
I
2
C™ modes. If both LATB<5> and LATB<4>
are clear, the module will work normally.
Work around
Clear the bits, LATB<5:4>, prior to enabling the
MSSP1 module in an I
2
C mode. Keep these bits
clear while using the module.
For operation in I
2
C modes, the TRISB<5:4>
bits should be set.
Affected Silicon Revisions
A2
X
A4
• Each time the SSPxIF is set, read the
SSPxBUF before the first rising clock edge of
the next byte being received.
Affected Silicon Revisions
A2
X
A4
X
2010 Microchip Technology Inc.
DS80436C-page 3
PIC18F46J50 FAMILY
3. Module: Enhanced Universal
Synchronous Asynchronous
Receiver Transmitter (EUSART)
In rare situations, when interrupts are enabled,
unexpected results may occur if:
• The EUSART is disabled (the SPEN bit,
RCSTAx<7> =
0)
• The EUSART is re-enabled (RCSTAx<7> =
1)
• A two-cycle instruction is executed immediately
after setting SPEN =
1
Work around
Add a 2 T
CY
delay after any instruction that re-
enables the EUSART module (sets SPEN =
1).
Refer to Example 1.
EXAMPLE 1:
RE-ENABLING A EUSART MODULE
;Initial conditions: SPEN = 0 (module disabled)
;To re-enable the module:
;Re-Initialize TXSTAx, BAUDCONx, SPBRGx, SPBRGHx registers (if needed)
;Re-Initialize RCSTAx register (if needed), but do not set SPEN = 1 yet
;Now enable the module, but add a 2-Tcy delay before executing any two-cycle
;instructions
bsf
RCSTA1, SPEN ;or RCSTA2 if EUSART2
nop
;1 Tcy delay
nop
;1 Tcy delay (two total)
;CPU may now execute 2 cycle instructions
Affected Silicon Revisions
A2
X
A4
X
DS80436C-page 4
2010 Microchip Technology Inc.
PIC18F46J50 FAMILY
4. Module: 10-Bit Analog-to-Digital
Converter (ADC)
When the A/D conversion clock select bits are set
for F
OSC
/2 (ADCON1<2:0> =
000),
the Integral
Linearity Error (EIL) parameter (A03) and Differen-
tial Linearity Error (EDL) parameter (A04) may
exceed data sheet specifications.
Work around
Select one of the alternate AD clock sources
shown in Table 3. The EIL and EDL parameters
are met for the other clocking options.
5. Module: Parallel Master Port (PMP)
When configured for Parallel Slave Port
(PMMODEH<1:0> =
0x
and PMPEN =
1),
the data
bus (PMD<7:0>) may not work correctly and
incorrect data could be captured into the PMDIN1L
register.
Work around
None.
Affected Silicon Revisions
A2
X
A4
TABLE 3:
ALTERNATE ADC SETTINGS
Clock Setting
F
OSC
/64
F
OSC
/16
F
OSC
/4
F
RC
F
OSC
/32
F
OSC
/8
ADCON1<2:0>
ADCS<2:0>
110
101
100
011
010
001
Affected Silicon Revisions
A2
X
A4
X
2010 Microchip Technology Inc.
DS80436C-page 5
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