Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state
FEATURES
•
3-state non-inverting outputs for
bus oriented applications
•
8-bit positive, edge-triggered
register
•
ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
•
Independent register and 3-state
buffer operation
•
Common 3-state output enable
input
•
Output capability; bus driver
•
I
CC
category: MSI
•
For AHC only:
operates with CMOS input levels
•
For AHCT only:
operates with TTL input levels
•
Specified from
−40
to +85 and +125
°C.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
≤
3.0 ns.
DESCRIPTION
74AHC574;
74AHCT574
The 74AHC/AHCT574 are high-speed Si-gate CMOS devices and are pin
compatible with low power Schottky TTL (LSTTL). They are specified in
compliance with JEDEC standard no. 7A.
The 74AHC/AHCT574 are octal D-type flip-flops featuring separate D-type
inputs for each flip-flop and 3-state outputs for bus oriented applications.
A clock (CP) and an output enable (OE) input are common to all flip-flops.
The 8 flip-flops will store the state of their individual D-inputs that meet the
set-up and hold times requirements on the LOW-to-HIGH CP transition.
When OE is LOW the contents of the 8 flip-flops are available at the outputs.
When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation
of the OE input does not affect the state of the flip-flops.
The ‘574’ is functionally identical to the ‘564’, but has non-inverting outputs.
The ‘574’ is functionally identical to the ‘374’, but has a different pinning.
TYPICAL
SYMBOL
t
PHL
/t
PLH
f
max
C
I
C
O
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
2. The condition is V
I
= GND to V
CC
.
1999 Jun 16
2
PARAMETER
propagation delay
CP to Q
n
maximum clock frequency
input capacitance
output capacitance
power dissipation
capacitance
C
L
= 50 pF; f = 1 MHz;
notes 1 and 2
C
L
= 15 pF; V
CC
= 5 V
V
I
= V
CC
or GND
130
4.0
4.0
10
130
4.0
4.0
12
MHz
pF
pF
pF
CONDITIONS
AHC
C
L
= 15 pF; V
CC
= 5 V
4.4
AHCT
4.4
ns
UNIT
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state
FUNCTION TABLE
See note 1.
INPUTS
OPERATING MODES
OE
Load and read register
Load register and disable outputs
L
L
H
H
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
Z = high-impedance OFF-state;
↑
= LOW-to-HIGH CP transition.
ORDERING INFORMATION
OUTSIDE NORTH
AMERICA
74AHC574D
74AHC574PW
74AHCT574D
74AHCT574PW
PINNING
PIN
1
2, 3, 4, 5, 6, 7, 8 and 9
10
11
19, 18, 17, 16, 15, 14, 13 and 12
20
OE
D
0
to D
7
GND
CP
Q
0
to Q
7
V
CC
SYMBOL
data inputs
ground (0 V)
PACKAGES
NORTH AMERICA
PINS
74AHC574D
74AHC574PW DH
74AHCT574D
74AHCT574PW DH
20
20
20
20
PACKAGE
SO
TSSOP
SO
TSSOP
MATERIAL
plastic
plastic
plastic
plastic
CP
↑
↑
↑
↑
D
n
I
h
l
h
74AHC574;
74AHCT574
INTERNAL
FLIP-FLOPS
L
H
L
H
OUTPUTS
Q
0
to Q
7
L
H
Z
Z
CODE
SOT163-1
SOT360-1
SOT163-1
SOT360-1
DESCRIPTION
3-state output enable input (active LOW)
clock input (LOW-to-HIGH, edge triggered)
3-state flip-flop outputs
DC supply voltage
1999 Jun 16
3
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1999 Jun 16
D0
D1
D2
D3
D
Q
FF1
CP
D
Q
FF2
CP
D
Q
FF3
CP
D
FF4
CP
Philips Semiconductors
Q
handbook, full pagewidth
Octal D-type flip-flop; positive edge-trigger; 3-state
D4
D5
D6
D7
D
Q
FF5
D
Q
FF6
D
FF7
CP
Q
D
Q
FF8
CP
CP
CP
5
CP
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
MNA449
74AHC574;
74AHCT574
Product specification
Fig.5 Logic diagram.
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