MC14538B
Dual Precision
Retriggerable/Resettable
Monostable Multivibrator
The MC14538B is a dual, retriggerable, resettable monostable
multivibrator. It may be triggered from either edge of an input pulse,
and produces an accurate output pulse over a wide range of widths, the
duration and accuracy of which are determined by the external timing
components, C
X
and R
X
. Output Pulse Width T = R
X
@
C
X
(secs)
R
X
=
W
C
X
= Farads
Features
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•
•
•
•
•
•
•
•
•
•
•
Unlimited Rise and Fall Time Allowed on the A Trigger Input
Pulse Width Range = 10
ms
to 10 s
Latched Trigger Inputs
Separate Latched Reset Inputs
3.0 Vdc to 18 Vdc Operational Limits
Triggerable from Positive (A Input) or Negative−Going Edge (B−Input)
Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
Pin−for−pin Compatible with MC14528B and CD4528B (CD4098)
Use the MC54/74HC4538A for Pulse Widths Less Than 10
ms
with
Supplies Up to 6 V
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input or Output Current
(DC or Transient) per Pin
Power Dissipation, per Package
(Note 1)
Operating Temperature Range
Storage Temperature Range
Lead Temperature
(8−Second Soldering)
Value
−0.5 to +18.0
−0.5 to V
DD
+ 0.5
±10
500
−55 to +125
−65 to +150
260
Unit
V
V
mA
SOIC−16
D SUFFIX
CASE 751B
SOIC−16WB
DW SUFFIX
CASE 751G
TSSOP−16
DT SUFFIX
CASE 948F
SOEIAJ−16
F SUFFIX
CASE 966
MARKING DIAGRAMS
16
14538BG
AWLYWW
1
SOIC−16
1
SOIC−16WB
16
14538BG
AWLYYWW
MAXIMUM RATINGS
(Voltages Referenced to V
SS
)
Symbol
V
DD
V
in
, V
out
I
in
, I
out
P
D
T
A
T
stg
T
L
16
16
14
538B
ALYWG
G
MC14538B
ALYWG
1
TSSOP−16
A
WL, L
YY, Y
WW, W
G or
G
SOEIAJ−16
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
1
mW
°C
°C
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
≤
(V
in
or V
out
)
≤
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
SS
or V
DD
). Unused outputs must be left open.
©
Semiconductor Components Industries, LLC, 2014
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
1
July, 2014 − Rev. 11
Publication Order Number:
MC14538B/D
MC14538B
PIN ASSIGNMENT
V
SS
C
X
/R
X
A
RESET A
A
A
B
A
Q
A
Q
A
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
V
SS
C
X
/R
X
B
RESET B
A
B
B
B
Q
B
Q
B
3
C
X
R
X
14
Q2
B
Q2
RESET
13
R
X
AND C
X
ARE EXTERNAL COMPONENTS.
V
DD
= PIN 16
V
SS
= PIN 8, PIN 1, PIN 15
10
9
4
5
1
A
Q1
B
Q1
RESET
6
7
2
BLOCK DIAGRAM
C
X
R
X
V
DD
V
DD
ONE−SHOT SELECTION GUIDE
100 ns
MC14528B
MC14536B
MC14538B
MC14541B
MC4538A*
*LIMITED OPERATING VOLTAGE (2 - 6 V)
TOTAL OUTPUT PULSE WIDTH RANGE
RECOMMENDED PULSE WIDTH RANGE
1
ms
10
ms
100
ms
1 ms
10 ms
100 ms
1s
10 s
23 HR
5 MIN.
12
11
A
15
ORDERING INFORMATION
Device
MC14538BDG
NLV14538BDG*
MC14538BDR2G
NLV14538BDR2G*
MC14538BDTR2G
NLV14538BDTR2G*
MC14538BDWG
NLV14538BDWG*
MC14538BDWR2G
NLV14538BDWR2G*
MC14538BFG
MC14538BFELG
Package
SOIC−16
(Pb−Free)
SOIC−16
(Pb−Free)
SOIC−16
(Pb−Free)
SOIC−16
(Pb−Free)
TSSOP−16
(Pb−Free)
TSSOP−16
(Pb−Free)
SOIC−16 WB
(Pb−Free)
SOIC−16 WB
(Pb−Free)
SOIC−16 WB
(Pb−Free)
SOIC−16 WB
(Pb−Free)
SOEIAJ−16
(Pb−Free)
SOEIAJ−16
(Pb−Free)
Shipping
†
48 Units / Rail
48 Units / Rail
2500 Units / Tape & Reel
2500 Units / Tape & Reel
2500 Units / Tape & Reel
2500 Units / Tape & Reel
47 Units / Rail
47 Units / Rail
1000 Units / Tape & Reel
1000 Units / Tape & Reel
50 Units / Rail
2000 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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2
MC14538B
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to V
SS
)
Characteristic
Output Voltage
V
in
= V
DD
or 0
“0” Level
Symbol
V
OL
V
DD
Vdc
5.0
10
15
5.0
10
15
5.0
10
15
“1” Level
(V
O
= 0.5 or 4.5 Vdc)
(V
O
= 1.0 or 9.0 Vdc)
(V
O
= 1.5 or 13.5 Vdc)
Output Drive Current
(V
OH
= 2.5 Vdc)
(V
OH
= 4.6 Vdc)
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
(V
OL
= 0.4 Vdc)
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
Input Current, Pin 2 or 14
Input Current, Other Inputs
Input Capacitance, Pin 2 or 14
Input Capacitance, Other Inputs
(V
in
= 0)
Quiescent Current
(Per Package)
Q = Low, Q = High
Quiescent Current, Active State
(Both) (Per Package)
Q = High, Q = Low
Total Supply Current at an external
load capacitance (C
L
) and at
external timing network (R
X
, C
X
)
(Note 3)
I
OH
Source
5.0
5.0
10
15
I
OL
5.0
10
15
15
15
−
−
5.0
10
15
5.0
10
15
5.0
10
–3.0
–0.64
–1.6
–4.2
0.64
1.6
4.2
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
±0.05
±0.1
−
−
5.0
10
20
2.0
2.0
2.0
–2.4
–0.51
–1.3
–3.4
0.51
1.3
3.4
−
−
−
−
−
−
−
−
−
−
–4.2
–0.88
–2.25
–8.8
0.88
2.25
8.8
±0.00001
±0.00001
25
5.0
0.005
0.010
0.015
0.04
0.08
0.13
−
−
−
−
−
−
−
±0.05
±0.1
−
7.5
5.0
10
20
0.20
0.45
0.70
–1.7
–0.36
–0.9
–2.4
0.36
0.9
2.4
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
±0.5
±1.0
−
−
150
300
600
2.0
2.0
2.0
mAdc
V
IH
5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
mAdc
− 55_C
Min
−
−
−
4.95
9.95
14.95
−
−
−
Max
0.05
0.05
0.05
−
−
−
1.5
3.0
4.0
Min
−
−
−
4.95
9.95
14.95
−
−
−
25_C
Typ
(Note 2)
0
0
0
5.0
10
15
2.25
4.50
6.75
Max
0.05
0.05
0.05
−
−
−
1.5
3.0
4.0
125_C
Min
−
−
−
4.95
9.95
14.95
−
−
−
Max
0.05
0.05
0.05
−
−
−
1.5
3.0
4.0
Vdc
Unit
Vdc
“1” Level
V
in
= 0 or V
DD
Input Voltage
(V
O
= 4.5 or 0.5 Vdc)
(V
O
= 9.0 or 1.0 Vdc)
(V
O
= 13.5 or 1.5 Vdc)
“0” Level
V
OH
Vdc
V
IL
Vdc
Sink
I
in
I
in
C
in
C
in
I
DD
mAdc
mAdc
pF
pF
mAdc
I
DD
mAdc
I
T
I
T
= (3.5 x 10
–2
) R
X
C
X
f + 4C
X
f + 1 x 10
–5
C
L
f
I
T
= (8.0 x 10
–2
) R
X
C
X
f + 9C
X
f + 2 x 10
–5
C
L
f
I
T
= (1.25 x 10
–1
) R
X
C
X
f + 12C
X
f + 3 x 10
–5
C
L
f
where: I
T
in
mA
(one monostable switching only),
where:
C
X
in
mF,
C
L
in pF, R
X
in k ohms, and
where:
f in Hz is the input frequency.
mAdc
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
External Timing Resistance
R
X
C
X
−
−
5.0
0
−
−
(Note 4)
kW
mF
External Timing Capacitance
No Limit
(Note 5)
4. The maximum usable resistance R
X
is a function of the leakage of the capacitor C
X
, leakage of the MC14538B, and leakage due to board
layout and surface resistance. Susceptibility to externally induced noise signals may occur for R
X
> 1 MW..
5. If C
X
> 15
mF,
use discharge protection diode per Fig. 11.
OPERATING CONDITIONS
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3
MC14538B
SWITCHING CHARACTERISTICS
(Note 6)
(C
L
= 50 pF, T
A
= 25_C)
All Types
Characteristic
Output Rise Time
t
TLH
= (1.35 ns/pF) C
L
+ 33 ns
t
TLH
= (0.60 ns/pF) C
L
+ 20 ns
t
TLH
= (0.40 ns/pF) C
L
+ 20 ns
Output Fall Time
t
THL
= (1.35 ns/pF) C
L
+ 33 ns
t
THL
= (0.60 ns/pF) C
L
+ 20 ns
t
THL
= (0.40 ns/pF) C
L
+ 20 ns
Propagation Delay Time
A or B to Q or Q
t
PLH
, t
PHL
= (0.90 ns/pF) C
L
+ 255 ns
t
PLH
, t
PHL
= (0.36 ns/pF) C
L
+ 132 ns
t
PLH
, t
PHL
= (0.26 ns/pF) C
L
+ 87 ns
Reset to Q or Q
t
PLH
, t
PHL
= (0.90 ns/pF) C
L
+ 205 ns
t
PLH
, t
PHL
= (0.36 ns/pF) C
L
+ 107 ns
t
PLH
, t
PHL
= (0.26 ns/pF) C
L
+ 82 ns
Input Rise and Fall Times
Reset
B Input
t
r
, t
f
Symbol
t
TLH
5.0
10
15
t
THL
5.0
10
15
t
PLH
,
t
PHL
5.0
10
15
5.0
10
15
5
10
15
5
10
15
5
10
15
t
WH
,
t
WL
t
rr
5.0
10
15
5.0
10
15
170
90
80
0
0
0
−
−
−
−
−
−
−
−
−
−
−
−
300
150
100
250
125
95
−
−
−
300
1.2
0.4
No Limit
85
45
40
−
−
−
−
−
−
−
−
−
ns
600
300
220
ns
500
250
190
15
5
4
1.0
0.1
0.05
ms
−
−
−
100
50
40
200
100
80
ns
−
−
−
100
50
40
200
100
80
ns
V
DD
Vdc
Min
Typ
(Note 7)
Max
Unit
ns
ms
A Input
−
Input Pulse Width
A, B, or Reset
Retrigger Time
ns
Output Pulse Width — Q or Q
Refer to Figures 8 and 9
C
X
= 0.002
mF,
R
X
= 100 kW
T
5.0
10
15
5.0
10
15
5.0
10
15
100
[(T
1
– T
2
)/T
1
]
5.0
10
15
198
200
202
9.3
9.4
9.5
0.91
0.92
0.93
−
−
−
210
212
214
9.86
10
10.14
0.965
0.98
0.99
±1.0
±1.0
±1.0
230
232
234
10.5
10.6
10.7
1.03
1.04
1.06
±5.0
±5.0
±5.0
ms
C
X
= 0.1
mF,
R
X
= 100 kW
ms
C
X
= 10
mF,
R
X
= 100 kW
s
Pulse Width Match between circuits in
the same package.
C
X
= 0.1
mF,
R
X
= 100 kW
%
6. The formulas given are for the typical characteristics only at 25_C.
7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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4
MC14538B
V
DD
R
X
2 (14)
C
X
V
ref1
N1
4 (12)
5 (11)
B
RESET
3 (13)
Q
R
S
RESET LATCH
Q
R
R
NOTE: Pins 1, 8 and 15 must
be externally grounded
V
SS
CONTROL
+
C1
-
ENABLE
V
ref2
ENABLE
+
C2
-
V
DD
P1
1 (15)
R
Q
OUTPUT
LATCH
S
Q
6 (10)
7 (9)
A
Figure 1. Logic Diagram
(1/2 of DevIce Shown)
V
DD
500 pF
I
D
R
X
V
SS
V
in
C
X
C
X
/R
X
Q
Q
Q′
Q′
C
L
V
SS
C
L
C
L
V
in
C
L
20 ns
90%
10%
20 ns
V
DD
0V
R
X
′
C
X
′
V
SS
0.1
mF
CERAMIC
A
B
RESET
A′
B′
RESET′
Figure 2. Power Dissipation Test Circuit and Waveforms
V
DD
INPUT CONNECTIONS
R
X
V
SS
PULSE
GENERATOR
PULSE
GENERATOR
PULSE
GENERATOR
C
X
C
X
/R
X
Q
Q
Q′
Q′
C
L
V
SS
C
L
C
L
C
L
R
X
′
C
X
′
*C
L
= 50 pF
V
SS
Characteristics
t
PLH
, t
PHL
, t
TLH
, t
THL
,
T, t
WH
, t
WL
t
PLH
, t
PHL
, t
TLH
, t
THL
,
T, t
WH
, t
WL
t
PLH(R)
, t
PHL(R)
,
t
WH
, t
WL
*Includes capacitance of probes,
wiring, and fixture parasitic.
NOTE: Switching test waveforms
for PG1, PG2, PG3 are shown
In Figure 4.
Reset
V
DD
V
DD
PG3
A
PG1
V
SS
PG1
B
V
DD
PG2
PG2
A
B
RESET
A′
B′
PG1 =
PG2 =
PG3 =
RESET′
Figure 3. Switching Test Circuit
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