There are two limitations on the power handling ability of
a transistor: average junction temperature and second
breakdown. Safe operating area curves indicate I
C
− V
CE
limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
The data of Figure 5 is based on T
J(pk)
= 150°C; T
C
is
variable depending on conditions. Second breakdown pulse
limits are valid for duty cycles to 10% provided T
J(pk)
≤
150°C. T
J(pk)
may be calculated from the data in Figure 6.
At high case temperatures, thermal limitations will reduce
the power that can be handled to values less than the
limitations imposed by second breakdown.
Figure 5. Forward Bias Safe Operating Area
r(t), TRANSIENT THERMAL
RESISTANCE (NORMALIZED)
1
0.7
0.5
0.3
0.2
0.1
0.07
0.05
0.03
0.02
0.01
0.01
D = 0.5
0.2
0.1
0.05
0.02
0.01
SINGLE PULSE
R
qJC(t)
= r(t) R
qJC
R
qJC
= 8.33°C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
1
T
J(pk)
- T
C
= P
(pk)
q
JC(t)
P
(pk)
t
1
t
2
DUTY CYCLE, D = t
1
/t
2
0.02 0.03
0.05
0.1
0.2 0.3
0.5
1
2 3
5
t, TIME (ms)
10
20
30
50
100
200 300
500
1k
Figure 6. Thermal Response
http://onsemi.com
3
MJD5731
TURN-ON PULSE
t
1
V
BE(off)
V
in
AP
PROX.
-11 V
t
2
t
3
51
C
jd
<< C
eb
0V
V
CC
t
1
≤
7.0 ns
100
≤
t
2
< 500
ms
t
3
< 15 ns
R
C
SCOPE
R
B
V
in
APPROX. + 9.0 V
DUTY CYCLE
≈
2.0%
+ 4.0 V
TURN-OFF PULSE
Figure 7. Switching Time Equivalent Circuit
1.0
0.5
0.3
t, TIME (
μ
s)
0.2
0.1
0.05
0.03
0.02
0.01
0.02 0.03
t
d
t
r
T
J
= 25°C
V
CC
= 200 V
I
C
/I
B
= 5.0
t, TIME (
μ
s)
5.0
3.0
2.0
t
f
1.0
0.5
0.3
0.2
0.1
0.05
0.02 0.03
t
s
T
J
= 25°C
V
CC
= 200 V
I
C
/I
B
= 5.0
0.05
0.1
0.2 0.3
0.5
I
C
, COLLECTOR CURRENT (AMPS)
1.0
2.0
0.05
0.1
0.2 0.3
0.5
I
C
, COLLECTOR CURRENT (AMPS)
1.0
2.0
Figure 8. Turn−On Resistive Switching Times
Figure 9. Resistive Turn−Off Switching Times
Test Circuit
V
CE
MONITOR
MJE171
50
INPUT
50
+
V
BB1
= 10 V
-
R
BB2
=
100
W
R
BB1
=
150
W
TUT
+
-
V
BB2
=
0
R
S
=
0.1
W
INPUT
VOLTAGE
100 mH
V
CC
= 20 V
I
C
MONITOR
Voltage and Current Waveforms
t
w
≈
3 ms
(SEE NOTE 1)
0V
-5 V
100 ms
0.63 A
COLLECTOR
CURRENT 0 V
V
CER
COLLECTOR
VOLTAGE
10 V
V
CE(sat)
Figure 10. Inductive Load Switching
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4
MJD5731
PACKAGE DIMENSIONS
DPAK
CASE 369C
ISSUE D
A
E
b3
4
C
A
B
c2
L3
1
D
2
3
DETAIL A
Z
H
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
MENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
DIM
A
A1
b
b2
b3
c
c2
D
E
e
H
L
L1
L2
L3
L4
Z
INCHES
MIN
MAX
0.086 0.094
0.000 0.005
0.025 0.035
0.030 0.045
0.180 0.215
0.018 0.024
0.018 0.024
0.235 0.245
0.250 0.265
0.090 BSC
0.370 0.410
0.055 0.070
0.108 REF
0.020 BSC
0.035 0.050
−−− 0.040
0.155
−−−
MILLIMETERS
MIN
MAX
2.18
2.38
0.00
0.13
0.63
0.89
0.76
1.14
4.57
5.46
0.46
0.61
0.46
0.61
5.97
6.22
6.35
6.73
2.29 BSC
9.40 10.41
1.40
1.78
2.74 REF
0.51 BSC
0.89
1.27
−−−
1.01
3.93
−−−
L4
b2
e
b
0.005 (0.13)
M
c
C
L2
GAUGE
PLANE
H
C
L
L1
DETAIL A
ROTATED 90 CW
5
SEATING
PLANE
A1
SOLDERING FOOTPRINT*
6.20
0.244
3.0
0.118
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
2.58
0.101
5.80
0.228
1.6
0.063
6.172
0.243
SCALE 3:1
mm
inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor
and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone:
303−675−2175 or 800−344−3860 Toll Free USA/Canada
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