STD5N95K5, STF5N95K5,
STP5N95K5, STU5N95K5
N-channel 950 V, 2 Ω typ., 3.5 A MDmesh™ K5
Power MOSFETs in DPAK, TO-220FP, TO-220 and IPAK
Datasheet - production data
TAB
2 3
1
Features
Order code
STD5N95K5
STF5N95K5
950 V
STP5N95K5
STU5N95K5
3
V
DS
R
DS(on)
max.
I
D
P
tot
70 W
DPAK
TAB
2
3
2.5 Ω
25 W
3.5 A
70 W
70 W
1
TO-220FP
TAB
1
2
TO-220
1
2
3
IPAK
Industry’s lowest R
DS(on)
x area
Industry’s best FoM (figure of merit)
Ultra-low gate charge
100% avalanche tested
Zener-protected
Figure 1: Internal schematic diagram
Applications
Switching applications
Description
These very high voltage N-channel Power
MOSFETs are designed using MDmesh™ K5
technology based on an innovative proprietary
vertical structure. The result is a dramatic
reduction in on-resistance and ultra-low gate
charge for applications requiring superior power
density and high efficiency.
Table 1: Device summary
Order code
STD5N95K5
STF5N95K5
STP5N95K5
STU5N95K5
5N95K5
Marking
Package
DPAK
TO-220FP
TO-220
IPAK
Tube
Packing
Tape and reel
January 2017
DocID024639 Rev 4
1/26
www.st.com
This is information on a product in full production.
Contents
STD5N95K5, STF5N95K5, STP5N95K5,
STU5N95K5
Contents
1
2
3
4
Electrical ratings ............................................................................. 3
Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 6
Test circuits ..................................................................................... 9
Package information ..................................................................... 10
4.1
4.2
4.3
4.4
4.5
4.6
DPAK (TO-252) type A2 package information................................. 11
DPAK (TO-252) type C2 package information ................................ 14
DPAK (TO-252) packing information ............................................... 17
TO-220FP package information ...................................................... 19
TO-220 type A package information................................................ 21
IPAK (TO-251) type A package information .................................... 23
5
Revision history ............................................................................ 25
2/26
DocID024639 Rev 4
STD5N95K5, STF5N95K5, STP5N95K5,
STU5N95K5
Electrical ratings
1
Electrical ratings
Table 2: Absolute maximum ratings
Value
Symbol
Parameter
DPAK, TO-220,
IPAK
±30
3.5
2.2
14
70
4.5
50
2500
-55 to 150
25
3.5
(1)
2.2
(1)
Unit
TO-220FP
V
A
A
A
W
V/ns
V/ns
V
°C
V
GS
I
D
I
D
I
DM
(2)
P
TOT
dv/dt
(3)
dv/dt
(4)
V
ISO
T
j
T
stg
Notes:
(1)
Limited
(2)
Pulse
(3)
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current pulsed
Total dissipation at T
C
= 25 °C
Peak diode recovery voltage slope
MOSFET dv/dt ruggedness
Insulation withstand voltage (RMS) from all three
leads to external heat sink (t=1 s; T
C
=25 °C)
Operating junction temperature range
Storage temperature range
by maximum junction temperature.
width limited by safe operating area.
I
SD
≤ 3.5 A, di/dt ≤ 100 A/μs, V
DS
(peak) ≤ V
(BR)DSS
DS
(4)
V
≤ 640 V
Table 3: Thermal data
Value
Symbol
R
thj-case
R
thj-amb
R
thj-pcb
(1)
Notes:
(1)
Parameter
DPAK
Thermal resistance junction-case
Thermal resistance junction-ambient
Thermal resistance junction-pcb
50
1.47
TO-220FP
5
62.5
TO-220
1.47
100
IPAK
Unit
°C/W
°C/W
°C/W
When mounted on 1 inch² FR-4, 2 Oz copper board
Table 4: Avalanche characteristics
Symbol
I
AR
E
AS
Parameter
Avalanche current, repetitive or not repetitive
(pulse width limited by T
jmax
)
Single pulse avalanche energy
(starting Tj = 25 °C, I
D
= I
AR
, V
DD
= 50 V)
Value
1
70
Unit
A
mJ
DocID024639 Rev 4
3/26
Electrical characteristics
STD5N95K5, STF5N95K5, STP5N95K5,
STU5N95K5
2
Electrical characteristics
T
C
= 25 °C unless otherwise specified
Table 5: On/off-state
Symbol
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Notes:
(1)
Defined
Parameter
Drain-source breakdown voltage
Zero gate voltage drain current
Gate body leakage current
Gate threshold voltage
Static drain-source on-resistance
Test conditions
V
GS
= 0 V, I
D
= 1 mA
V
DS
= 950 V, V
GS
= 0 V
V
DS
= 950 V, V
GS
= 0 V
T
C
= 125 °C
(1)
V
GS
= ±20 V, V
DS
= 0 V
V
DS
= V
GS
, I
D
= 100 µA
V
GS
= 10 V, I
D
= 1.5 A
Min.
950
Typ.
Max.
Unit
V
1
50
±10
3
4
2
5
2.5
µA
µA
µA
V
Ω
by design, not subject to production test.
Table 6: Dynamic
Symbol
C
iss
C
oss
C
rss
C
o(tr)
(1)
C
o(er)
(2)
R
g
Q
g
Q
gs
Q
gd
Parameter
Input capacitance
Output capacitance
Reverse transfer capacitance
Equivalent capacitance time
related
Equivalent capacitance energy
related
Intrinsic gate resistance
Total gate charge
Gate-source charge
Gate-drain charge
V
GS
= 0 V,
V
DS
= 0 to 760 V
f = 1 MHz open drain
V
DD
= 760 V, I
D
= 3.5 A
V
GS
= 10 V
(see
Figure 19: "Test
circuit for gate charge
behavior")
V
DS
= 100 V, f = 1 MHz,
V
GS
= 0 V
Test conditions
Min.
-
-
-
-
-
-
-
-
-
Typ.
220
17
1
30
11
17
12.5
2
10
Max.
-
-
-
-
-
-
-
-
-
Unit
pF
pF
pF
pF
pF
Ω
nC
nC
nC
Notes:
(1)
C
o(tr)
is a constant capacitance value that gives the same charging time as C
oss
while V
DS
is rising from 0 to
80% V
DSS
.
(2)
C
o(er)
is a constant capacitance value that gives the same stored energy as C
oss
while V
DS
is rising from 0 to
80% V
DSS
.
4/26
DocID024639 Rev 4
STD5N95K5, STF5N95K5, STP5N95K5,
STU5N95K5
Table 7: Switching times
Symbol
t
d(on)
t
r
t
d(off)
t
f
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Test conditions
V
DD
= 475 V, I
D
= 1.75 A,
R
G
= 4.7 Ω
V
GS
= 10 V
(see
Figure 18: "Test circuit for
resistive load switching times"
and
Figure 23: "Switching time
waveform")
Table 8: Source-drain diode
Symbol
I
SD
I
SDM
V
SD
(1)
t
rr
Q
rr
I
RRM
t
rr
Q
rr
I
RRM
Parameter
Source-drain current
Source-drain current
(pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
I
SD
= 3.5 A, V
GS
= 0 V
Test conditions
Electrical characteristics
Min.
-
-
-
-
Typ.
12
16
32
25
Max.
-
-
-
-
Unit
ns
ns
ns
ns
Min.
-
-
-
-
-
-
-
-
-
Typ.
Max.
3.5
14
1.5
Unit
A
A
V
ns
µC
A
ns
µC
A
I
SD
= 3.5 A, di/dt = 100 A/µs,
V
DD
= 60 V
(see
Figure 20: "Test circuit
for inductive load switching
and diode recovery times")
I
SD
= 3.5 A, di/dt = 100 A/µs,
V
DD
= 60 V, T
j
= 150 °C
(see
Figure 20: "Test circuit
for inductive load switching
and diode recovery times")
330
2.2
13
525
3.2
12
Notes:
(1)
Pulsed:
pulse duration = 300 µs, duty cycle 1.5%
Table 9: Gate-source Zener diode
Symbol
V
(BR)GSO
Parameter
Gate-source breakdown voltage
Test conditions
I
GS
= ± 1 mA, I
D
= 0 A
Min
30
Typ.
-
Max
-
Unit
V
The built-in back-to-back Zener diodes are specifically designed to enhance the ESD
performance of the device. The Zener voltage facilitates efficient and cost-effective device
integrity protection,thus eliminating the need for additional external componentry.
DocID024639 Rev 4
5/26
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