STW70N65M2
N-channel 650 V, 0.039 Ω typ., 63 A MDmesh™ M2
Power MOSFET in a TO-247 package
Datasheet - production data
Features
Order code
STW70N65M2
V
DS
650 V
R
DS(on)
max.
0.046 Ω
I
D
63 A
3
2
1
Extremely low gate charge
Excellent output capacitance (C
OSS
) profile
100% avalanche tested
Zener-protected
TO-247
Applications
Switching applications
Figure 1: Internal schematic diagram
D(2)
Description
This device is an N-channel Power MOSFET
developed using MDmesh™ M2 technology.
Thanks to its strip layout and an improved vertical
structure, the device exhibits low on-resistance
and optimized switching characteristics,
rendering it suitable for the most demanding high
efficiency converters.
G(1)
S(3)
AM15572v1_no_tab
Table 1: Device summary
Order code
STW70N65M2
Marking
70N65M2
Package
TO-247
Packaging
Tube
February 2016
DocID028962 Rev 1
1/12
www.st.com
This is information on a product in full production.
Contents
STW70N65M2
Contents
1
2
3
4
5
Electrical ratings ............................................................................. 3
Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 6
Test circuits ..................................................................................... 8
Package mechanical data ............................................................... 9
4.1
TO-247 package information ............................................................. 9
Revision history ............................................................................ 11
2/12
DocID028962 Rev 1
STW70N65M2
Electrical ratings
1
Electrical ratings
Table 2: Absolute maximum ratings
Symbol
V
GS
I
D
I
D
I
DM
(1)
Parameter
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed)
Total dissipation at T
C
= 25 °C
Peak diode recovery voltage slope
MOSFET dv/dt ruggedness
Storage temperature range
Operating junction temperature range
Value
± 25
63
40
252
446
15
50
- 55 to 150
Unit
V
A
A
A
W
V/ns
V/ns
°C
P
TOT
dv/dt
dv/dt
T
stg
T
j
Notes:
(1)
(2)
(3)
(2)
(3)
Pulse width limited by safe operating area.
I
SD
≤ 63 A, di/dt ≤ 400 A/µs; V
DS peak
< V
(BR)DSS
, V
DD
= 400 V
V
DS
≤ 520 V
Table 3: Thermal data
Symbol
R
thj-case
R
thj-amb
Parameter
Thermal resistance junction-case max
Thermal resistance junction-ambient max
Table 4: Avalanche characteristics
Symbol
I
AR
E
AS
Parameter
Avalanche current, repetetive or not repetetive (pulse width
limited by T
jmax
)
Single pulse avalanche energy (starting T
j
= 25 °C, I
D
= I
AR
,
V
DD
= 50 V)
Value
4
3500
Unit
A
mJ
Value
0.28
50
Unit
°C/W
°C/W
DocID028962 Rev 1
3/12
Electrical characteristics
STW70N65M2
2
Electrical characteristics
(T
C
= 25 °C unless otherwise specified)
Table 5: On/off states
Symbol
V
(BR)DSS
Parameter
Drain-source breakdown
voltage
Zero gate voltage drain
current
Gate-body leakage
current
Gate threshold voltage
Static drain-source
on-resistance
Test conditions
V
GS
= 0 V, I
D
= 1 mA
V
GS
= 0 V, V
DS
= 650 V
V
GS
= 0 V, V
DS
= 650 V,
(1)
T
C
= 125 °C
V
DS
= 0 V, V
GS
= ± 25 V
V
DS
= V
GS
, I
D
= 250 µA
V
GS
= 10 V, I
D
= 31.5 A
2
3
0.039
Min.
650
1
100
±5
4
0.046
Typ.
Max.
Unit
V
µA
µA
µA
V
Ω
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Notes:
(1)
Defined by design, not subject to production test.
Table 6: Dynamic
Symbol
C
iss
C
oss
C
rss
C
oss eq.
R
G
Q
g
Q
gs
Q
gd
Notes:
(1)
(1)
Parameter
Input capacitance
Output capacitance
Reverse transfer
capacitance
Equivalent output
capacitance
Intrinsic gate resistance
Total gate charge
Gate-source charge
Gate-drain charge
Test conditions
Min.
-
Typ.
5140
208
2.9
520
3
Max.
-
-
-
-
-
-
-
-
Unit
pF
pF
pF
pF
Ω
nC
nC
nC
V
DS
= 100 V, f = 1 MHz,
V
GS
= 0 V
-
-
V
DS
= 0 V to 520 V, V
GS
= 0 V
f = 1 MHz, I
D
=0 A
V
DD
= 520 V, I
D
= 63 A,
V
GS
= 10 V (see
Figure 15:
"Test circuit for gate charge
behavior")
-
-
-
-
-
117
21.5
51
C
oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C
oss
when V
DS
increases from 0 to 80% V
DSS
Table 7: Switching times
Symbol
t
d(on)
t
r
t
d(off)
t
f
Parameter
Turn-on delay time
Rise time
Turn-off-delay time
Fall time
Test conditions
V
DD
= 325 V, I
D
= 31.5 A
R
G
= 4.7 Ω, V
GS
= 10 V
(see
Figure 14: "Test circuit for
resistive load switching times"
and
Figure 19: "Switching time
waveform")
Min.
-
-
-
-
Typ.
24
22
134
11
Max.
-
-
-
-
Unit
ns
ns
ns
ns
4/12
DocID028962 Rev 1
STW70N65M2
Table 8: Source drain diode
Symbol
I
SD
I
SDM
V
SD
t
rr
Q
rr
I
RRM
t
rr
Q
rr
I
RRM
Notes:
(1)
(2)
(1)
Electrical characteristics
Parameter
Source-drain current
Source-drain current
(pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
V
GS
= 0 V, I
SD
= 63 A
I
SD
= 63 A, di/dt = 100 A/µs,
V
DD
= 60 V
(see
Figure 16: "Test circuit for
inductive load switching and
diode recovery times")
I
SD
= 63 A, di/dt = 100 A/µs,
V
DD
= 60 V, T
j
= 150 °C
(see
Figure 16: "Test circuit for
inductive load switching and
diode recovery times")
Test conditions
Min.
-
-
-
-
-
-
-
-
-
584
14.5
50.5
725
20
55.5
Typ.
Max.
63
252
1.6
Unit
A
A
V
ns
µC
A
ns
µC
A
(2)
Pulse width is limited by safe operating area
Pulse test: pulse duration = 300 µs, duty cycle 1.5%
DocID028962 Rev 1
5/12
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