Low Skew CMOS PLL Clock Drivers, 3-State
55, 70, 100, 133, and 160 MHz Versions
MC88915T
The MC88915T Clock Driver utilizes phase-locked loop (PLL) technology to
lock its low skew outputs frequencies and phase onto an input reference clock. It
is designed to provide clock distribution for high performance PCs and
workstations. For a 3.3 V version, see the MC88LV915T data sheet.
The PLL allows the high current, low skew outputs to lock onto a single clock
input and distribute it to multiple components on a board. The PLL also allows
the MC88915T to multiply a low frequency input clock and distribute it locally at
a higher (2X) system frequency. Multiple 88915s can lock onto a single reference
clock, ideal for applications when a central system clock must be distributed
synchronously to multiple boards (see
Figure 9).
Five “Q” outputs (Q0–Q4) are provided with less than 500 ps skew between
their rising edges. The Q5 output is inverted (180° phase shift) from the “Q”
outputs. The 2X_Q output runs at twice the “Q” output frequency, while the
Q/2 runs at 1/2 the “Q” frequency.
LOW SKEW CMOS
The VCO is designed to run optimally between 20 MHz and the 2X_Q f
max
PLL CLOCK DRIVER
specification. The wiring diagrams in
Figure 7
detail the different feedback
configurations, creating specific input/output frequency relationships. Possible
frequency ratios of the “Q” outputs to the SYNC input are 2:1, 1:1, and 1:2.
The FREQ_SEL pin provides one bit programmable divide-by in the feedback
path of the PLL. It selects between divide-by-1 and divide-by-2 of the VCO before
its signal reaches the internal clock distribution section of the chip (see
2
). In most
applications FREQ_SEL should be held high (÷1). If a low frequency reference
FN SUFFIX
clock input is used, holding FREQ_SEL low (÷2) allows the VCO to run in its
28-LEAD PLCC PACKAGE
optimal range (>20 MHz and >40 MHz for the TFN133 version).
CASE 766-02
In normal phase-locked operation the PLL_EN pin is held high. Pulling the
PLL_EN pin low disables the VCO and puts the 88915 in a static “test mode.” In
this mode, there is no frequency limitation on the input clock, necessary for a low
frequency board test environment. The second SYNC input can be used as a test
clock input to further simplify board-level testing (see
APPLICATIONS
INFORMATION FOR ALL VERSIONS on page 12).
EI SUFFIX
Pulling the OE/RST pin low puts the clock outputs 2X_Q, Q0–Q4, Q5, and Q/
28-LEAD PLCC PACKAGE
Pb-FREE PACKAGE
2 into a high impedance state (3-state). After the
CASE 766-02
OE/RST pin goes back high Q0–Q4, Q5, and Q/2 will be reset in the low state,
with 2X_Q being the inverse of the selected SYNC input. Assuming PLL_EN is
low, the outputs will remain reset until the 88915 sees a SYNC input pulse.
A lock indicator output (LOCK) will go high when the loop is in steady-state phase and frequency lock. The LOCK output will
go low if phase-lock is lost, or when the PLL_EN pin is low. The LOCK output will go high no later than 10 ms after the 88915
sees a SYNC signal and full 5.0 V V
CC
.
MC88915TFN70
MC88915TFN100
MC88915TFN133
MC88915TFN160
MC88915TFN55
Features
•
•
•
•
•
•
•
•
•
Five outputs (Q0–Q4) with output-output skew < 500 ps, each being phase and frequency locked to the SYNC input
The phase variation from part-to-part between the SYNC and FEEDBACK inputs is less than 550 ps (derived from the t
PD
specification, defining the part-to-part skew).
Input/output phase-locked frequency ratios of 1:2, 1:1, and 2:1 are available
Input frequency range from 5 MHz – 2X_Q f
max
specification (10 MHz – 2X_Q f
max
for the TFN133 version)
Additional outputs available at 2X and +2 the system “Q” frequency. Also, a Q (180° phase shift) output available
All outputs have ±36 mA drive (equal high and low) at CMOS levels, and can drive either CMOS or TTL inputs. All inputs are
TTL-level compatible. ±88 mA I
OL
/I
OH
specifications guarantee 50
Ω
transmission line switching on the incident edge.
Test mode pin (PLL_EN) provided for low frequency testing. Two selectable CLOCK inputs for test or redundancy purposes.
All outputs can go into high impedance (3-state) for board test purposes.
Lock indicator (LOCK) accuracy indicates a phase-locked state.
28-lead Pb-free package available.
IDT™ / ICS™
CMOS PLL CLOCK DRIVERS
1
MC88915TREV 7 JULY 10, 2007
MC88915T
LOW SKEW CMOS PLL CLOCK DRIVERS, 3-STATE
OE/RST V
CC
Q5 GND Q4 V
CC
2X_Q
4
FEEDBACK
REF_SEL
SYNC[0]
V
CC
(AN)
RC1
GND(AN)
SYNC[1]
5
6
7
8
9
10
11
12
13 14
15 16
17 18
3
2
1
28
27 26
25
24
23
22
21
20
19
Q/2
GND
Q3
V
CC
Q2
GND
LOCK
FREQ_SEL GND Q0 V
CC
Q1 GND PLL_EN
Figure 1. Pinout: 28-Lead PLCC
(Top View)
Table 1. Pin Summary
Pin Name
SYNC[0]
SYNC[1]
REF_SEL
FREQ_SEL
FEEDBACK
RC1
Q(0–4)
Q5
2x_Q
Q/2
LOCK
OE/RST
PLL_EN
V
CC
, GND
Number
1
1
1
1
1
1
5
1
1
1
1
1
1
11
I/O
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Output
Input
Input
Reference clock input
Reference clock input
Chooses reference between SYNC[0] and SYNC[1]
Doubles VCO internal frequency (low)
Feedback input to phase detector
Input for external RC network
Clock output (locked to SYNC)
Inverse of clock output
2 x clock output (Q) frequency (synchronous)
Clock output (Q) frequency
÷
2 (synchronous)
Indicates phase lock has been achieved (high when locked)
Output enable/asynchronous reset (active low)
Disables phase-lock for low frequency testing
Power and ground pins (note pins 8 and 10 are “analog” supply pins
for internal PLL only)
Function
IDT™ / ICS™
CMOS PLL CLOCK DRIVERS
2
MC88915TREV 7 JULY 10, 2007
MC88915T
LOW SKEW CMOS PLL CLOCK DRIVERS, 3-STATE
LOCK
FEEDBACK
SYNC (0)
0
SYNC (1)
REF_SEL
1
M
U
X
PHASE/FREQ
DETECTOR
CHARGE PUMP/LOOP
FILTER
VOLTAGE
CONTROLLED
OSCILLATOR
EXTERNAL REC NETWORK
(RC1 PIN)
PLL_EN
0
MUX
1
2x_Q
(÷1)
D
1
M
U
X
CP
R
Q
Q
Q0
(÷2)
DIVIDE
BY TWO
0
D
CP
R
Q
Q1
FREQ_SEL
OE/RST
D
CP
R
Q
Q2
D
CP
R
Q
Q3
D
CP
R
Q
Q4
D
CP
R
Q
Q5
Figure 2. MC88915T Block Diagram
(All Versions)
D
Q/2
IDT™ / ICS™
CMOS PLL CLOCK DRIVERS
3
MC88915TREV 7 JULY 10, 2007
MC88915T
LOW SKEW CMOS PLL CLOCK DRIVERS, 3-STATE
MC88915TFN55 AND MC88915TFN70
Table 2. SYNC Input Timing Requirements
Symbol
t
RISE/FALL
, SYNC Inputs
t
CYCLE
, SYNC Inputs
Parameter
Rise/Fall Time, SYNC Inputs from 0.8 to 2.0 V
Input Clock Period SYNC Inputs
Minimum
TFN70
—
28.5
(1)
TFN55
—
36.0
(1)
50% ± 25%
Maximum
3.0
200
(2)
Unit
ns
ns
Duty Cycle SYNC Inputs Input Duty Cycle SYNC Inputs
1. These t
CYCLE
minimum values are valid when “Q” output is fed back and connected to the FEEDBACK pin. This is the configuration shown
in
Figure 7b.
2.Information in
Table 22
and in Note 3 of the AC specification notes describe this specification with its limits depending on what output is fed
back, and if FREQ_SEL is high or low.
Table 3. DC Electrical Characteristics
(Voltages Referenced to GND)
T
A
= –40°C to +85°C for 55 MHz Version; T
A
= 0°C to +70°C for 70 MHz Version; V
CC
= 5.0 V ± 5%
Symbol
V
IH
V
IL
V
OH
V
OL
I
in
I
CCT
I
OLD
I
OHD
I
CC
I
OZ
Maximum Quiescent Supply Current (per Package)
Maximum 3-State Leakage Current
Parameter
Minimum High-Level Input Voltage
Maximum Low-Level Input Voltage
Minimum High-Level Output Voltage
Test Conditions
V
out
= 0.1 V or V
CC
– 0.1 V
V
out
= 0.1 V or V
CC
– 0.1 V
V
in
= V
IH
or V
IL
I
OH
= –36
Maximum Low-Level Output Voltage
mA
(1)
(1)
V
CC
V
4.75
5.25
4.75
5.25
4.75
5.25
4.75
5.25
5.25
5.25
5.25
5.25
5.25
5.25
Target
Limit
2.0
2.0
0.8
0.8
4.01
4.51
0.44
0.44
± 1.0
2.0
88
–88
1.0
± 50
Unit
V
V
V
V
in
= V
IH
or V
IL
I
OH
= 36 mA
V
I
= V
CC
or GND
V
I
= V
CC
– 2.1 V
V
OLD
= 1.0 V Maximum
V
OHD
= 3.85 V Minimum
V
I
= V
CC
or GND
V
I
= V
IH
or V
IL
; V
O
= V
CC
or GND
V
µA
mA
mA
mA
mA
µA
Maximum Input Leakage Current
Maximum I
CC
/Input
Minimum Dynamic Output Current
1. Maximum test duration is 2.0 ms, one output loaded at a time.
Table 4. Capacitance and Power Specifications
Symbol
C
IN
C
PD
PD
1(1)
PD
2(1)
Input Capacitance
Power Dissipation Capacitance
Power Dissipation @ 50 MHz with 50
Ω
Thevenin Termination
Power Dissipation @ 50 MHz with 50
Ω
Parallel Termination to GND
Parameter
Typical Values
4.5
40
23 mW/Output
184 mW/Device
57 mW/Output
456 mW/Device
Unit
pF
pF
mW
mW
Conditions
V
CC
= 5.0 V
V
CC
= 5.0 V
V
CC
= 5.0 V
T = 25°C
V
CC
= 5.0 V
T = 25°C
1. PD
1
nd PD
2
mW/Output numbers are for a “Q” output.
IDT™ / ICS™
CMOS PLL CLOCK DRIVERS
4
MC88915TREV 7 JULY 10, 2007
MC88915T
LOW SKEW CMOS PLL CLOCK DRIVERS, 3-STATE
MC88915TFN55 AND MC88915TFN70
(Continued)
Table 5. Frequency Specifications
(T
A
= –40°C to +85 °C, V
CC
= 5.0 V ± 5%)
Symbol
f
max(1)
Parameter
Maximum Operating Frequency (2X_Q Output)
Maximum Operating Frequency (Q0–Q4, Q5 Output)
Guaranteed Minimum
TFN70
70
35
TFN55
55
27.5
Unit
MHz
MHz
1. Maximum Operating Frequency is guaranteed with the part in a phase-locked condition, and all outputs loaded with 50
Ω
terminated
to V
CC
/2.
Table 6. AC Characteristics
(T
A
= –40°C to +85°C, V
CC
= 5.0 V ± 5%, Load = 50
Ω
Terminated to V
CC
/2)
Symbol
t
RISE/FALL
Outputs
t
RISE/FALL
2X_Q Output
Parameter
Rise/Fall Time, All Outputs
(Between 0.2 V
CC
and 0.8 V
CC
)
Rise/Fall Time into a 20 pF Load, with Termination
Specified in Note
(2)
0.5 t
CYCLE
– 0.5
(2)
0.5 t
CYCLE
+ 0.5
(2)
(2)
66 MHz 0.5 t
0.5 t
CYCLE
+ 0.5
(2)
CYCLE
– 0.5
50 MHz 0.5 t
CYCLE
– 1.0 0.5 t
CYCLE
+ 1.0
40 MHz 0.5 t
CYCLE
– 1.5 0.5 t
CYCLE
+ 1.5
(2)
50 – 65 MHz 0.5 t
0.5 t
CYCLE
+ 1.0
(2)
CYCLE
– 1.0
40 – 49 MHz 0.5 t
CYCLE
– 1.5 0.5 t
CYCLE
+ 1.5
66 – 70 MHz 0.5 t
CYCLE
– 0.5 0.5 t
CYCLE
+ 0.5
Min
1.0
0.5
Max
2.5
1.6
Unit
ns
ns
ns
ns
Condition
Into a 50
Ω
Load
Terminated to V
CC
/2
t
RISE
: 0.8 V – 2.0 V
t
FALL
: 2.0 V – 0.8 V
Into a 50
Ω
Load
Terminated to V
CC
/2
Must Use Termination
Specified in Note
(2)
Output Pulse Width: Q0, Q1, Q2, Q4, Q4,
t
PULSEWIDTH(1)
(Q0–Q4, Q5, Q/2) Q5, Q/2 @ V
CC
/2
t
PULSEWIDTH(1)
(2X_Q Output)
t
PULSEWIDTH(1)
(2X_Q Output)
Output Pulse Width:
2X_Q @ 1.5 V
Output Pulse Width:
2X_Q @ V
CC
/2
ns
Into a 50
Ω
Load
Terminated to V
CC
/2
See Note
(4)
and
Figure 4
for Detailed
Explanation
SYNC Input to Feedback Delay
t
PD(1),(3)
SYNC Feedback (Measured at SYNC0 or 1
and FEEDBACK Input Pins)
(With 1 MΩ from RC1 to An V
CC
)
–1.05
+1.25
–0.40
+3.25
500
(With 1 MΩ from RC1 to An GND)
ns
t
SKEWr(4)
(Rising)
(5)
t
SKEWf(1),(4)
(Falling)
t
SKEWall(1),(4)
Output-to-Output Skew Between Outputs Q0–Q4,
Q/2 (Rising Edges Only)
Output-to-Output Skew Between Outputs Q0–Q4
(Falling Edges Only)
Output-to-Output Skew 2X_Q, Q/2, Q0–Q4 Rising,
Q5 Falling
Time Required to Acquire Phase-Lock from Time
SYNC Input Signal is Received
Output Enable Time OE/RST to 2X_Q, Q0–Q4,
Q5, and Q/2
Output Disable Time OE/RST to 2X_Q, Q0–Q4,
Q5, and Q/2
—
ps
All Outputs into a
Matched 50
Ω
Load
Terminated to V
CC
/2
All Outputs into a
Matched 50
Ω
Load
Terminated to V
CC
/2
All Outputs into a
Matched 50
Ω
Load
Terminated to V
CC
/2
Also Time to LOCK
Indicator High
Measured with the
PLL_EN Pin Low
Measured with the
PLL_EN Pin Low
—
500
ps
—
750
ps
t
LOCK(5)
t
PZL
t
PHZ
, t
PLZ
1.
2.
3.
4.
5.
1.0
3.0
3.0
10
14
14
ms
ns
ns
These specifications are not tested. They are guaranteed by statistical characterization. See AC specification Note 1.
t
CYCLE
in this spec is 1/Frequency at which the particular output is running.
The t
PD
specification’s min/max values may shift closer to zero if a larger pullup resistor is used.
Under equally loaded conditions and at a fixed temperature and voltage.
With V
CC
fully powered on, and an output properly connected to the FEEDBACK pin. t
LOCK
maximum is with C1 = 0.1
µF,
t
LOCK
minimum is
with C1 = 0.01
µF.
IDT™ / ICS™
CMOS PLL CLOCK DRIVERS
5
MC88915TREV 7 JULY 10, 2007
Automotive Electronics
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