M28256
256 Kbit (32Kb x8) Parallel EEPROM
with Software Data Protection
PRELIMINARY DATA
FAST ACCESS TIME:
– 90ns at 5V
– 120ns at 3V
SINGLE SUPPLY VOLTAGE:
– 5V
±
10% for M28256
– 2.7V to 3.6V for M28256-xxW
LOW POWER CONSUMPTION
FAST WRITE CYCLE:
– 64 Bytes Page Write Operation
– Byte or Page Write Cycle
ENHANCED END of WRITE DETECTION:
– Data Polling
– Toggle Bit
STATUS REGISTER
HIGH RELIABILITY DOUBLE POLYSILICON,
CMOS TECHNOLOGY:
– Endurance >100,000 Erase/Write Cycles
– Data Retention >10 Years
JEDEC APPROVED BYTEWIDE PIN OUT
ADDRESS and DATA LATCHED ON-CHIP
SOFTWARE DATA PROTECTION
28
1
PDIP28 (BS)
PLCC32 (KA)
28
1
SO28 (MS)
300 mils
TSOP28 (NS)
8 x13.4mm
Figure 1. Logic Diagram
VCC
DESCRIPTION
The M28256 and M28256-Ware 32K x8 low power
Parallel EEPROM fabricatedwith STMicroelectron-
ics proprietary double polysilicon CMOS technol-
ogy.
Table 1. Signal Names
A0-A14
DQ0-DQ7
W
E
G
V
CC
V
SS
Address Input
Data Input / Output
Write Enable
Chip Enable
Output Enable
Supply Voltage
Ground
15
A0-A14
8
DQ0-DQ7
W
E
G
M28256
VSS
AI01885
January 1999
This is preliminary information on a new product now in developmentor undergoing evaluation . Detail s are subject to change without notice.
1/21
M28256
Figure 2A. DIP Pin Connections
Figure 2B. LCC Pin Connections
AI01886
AI01887
Warning:
NC = Not Connected, DU = Don’t Use.
Figure 2C. SO Pin Connections
Figure 2D. TSOP Pin Connections
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
M28256
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AI01888
VCC
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
G
A11
A9
A8
A13
W
VCC
A14
A12
A7
A6
A5
A4
A3
22
DQ1
DQ2
VSS
DU
DQ3
DQ4
DQ5
21
28
1
M28256
15
14
7
8
AI01889
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
28
2
27
3
26
4
25
5
24
6
23
7
22
M28256
8
21
9
20
10
19
11
18
12
17
13
16
14
15
VCC
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
A6
A5
A4
A3
A2
A1
A0
NC
DQ0
A7
A12
A14
DU
VCC
W
A13
1 32
A8
A9
A11
NC
G
A10
E
DQ7
DQ6
9
M28256
25
17
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
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M28256
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
T
STG
V
CC
V
IO
V
I
V
ESD
Parameter
Ambient Operating Temperature
Storage Temperature Range
Supply Voltage
Input/Output Voltage
Input Voltage
Electrostatic Discharge Voltage (Human Body model)
(3)
(2)
Value
– 40 to 85
– 65 to 150
– 0.3 to 6.5
– 0.3 to V
CC
+0.6
– 0.3 to 6.5
4000
Unit
°C
°
C
V
V
V
V
Notes:
1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. Depends on range.
3. 100pF through 1500Ω; MIL-STD-883C, 3015.7
Figure 3. Block Diagram
E
G
W
VPP GEN
RESET
CONTROL LOGIC
X DECODE
A6-A14
(Page Address)
ADDRESS
LATCH
256K ARRAY
A0-A5
ADDRESS
LATCH
Y DECODE
SENSE AND DATA LATCH
I/O BUFFERS
PAGE LOAD
TIMER STATUS
TOGGLE BIT
DATA POLLING
AI01697
DQ0-DQ7
3/21
M28256
Table 3. Operating Modes
(1)
Mode
Read
Write
Standby / Write Inhibit
Write Inhibit
Write Inhibit
Output Disable
Notes:
1. X = V
IH
or V
IL.
E
V
IL
V
IL
V
IH
X
X
X
G
V
IL
V
IH
X
X
V
IL
V
IH
W
V
IH
V
IL
X
V
IH
X
X
DQ0 - DQ7
Data Out
Data In
Hi-Z
Data Out or Hi-Z
Data Out or Hi-Z
Hi-Z
DESCRIPTION
(Cont’d)
The devices offer fast access time with low power
dissipation and requires a 5V or 3V power supply.
The circuit has been designed to offer a flexible
microcontroller interface featuring both hardware
and software handshaking with Data Polling and
Toggle Bit and access to a status register. The
devices support a 64 byte page write operation. A
Software Data Protection (SDP) is also possible
using the standard JEDEC algorithm.
PIN DESCRIPTION
Addresses (A0-A14).
The address inputs select
an 8-bit memory location during a read or write
operation.
Chip Enable (E).
The chip enable input must be
low to enable all read/write operations.When Chip
Enable is high, power consumption is reduced.
Output Enable (G).
The Output Enable input con-
trols the data output buffers and is used to initiate
read operations.
Data In/ Out (DQ0- DQ7).
Data is written to or read
from the memory through the I/O pins.
Write Enable (W).
The Write Enable input controls
the writing of data to the memory.
OPERATIONS
Write Protection
In order to prevent data corruption and inadvertent
write operations; an internal V
CC
comparatorinhib-
its Write operations if V
CC
is below VWI (see Table
7 andTable 9).Access to the memoryin write mode
is allowed after a power-up as specified in Table 7
and Table 9.
Read
The device is accessed like a static RAM. When E
and G are low with W high, the data addressed is
presented on the I/O pins. The I/O pins are high
impedance when either G or E is high.
Write
Write operations are initiated when both W and E
are low and G is high.The device supports both E
and W controlled write cycles. The Address is
latched by the falling edge of E or W which ever
occurs last and the Data on the rising edge of E or
W which ever occurs first. Once initiated the write
operation is internally timed until completion and
the status of the Data Polling and the Toggle Bit
functions on DQ7 and DQ6 is controlled accord-
ingly.
Page Write
Page write allows up to 64 bytes within the same
page to be consecutively latched into the memory
prior to initiating a programming cycle. All bytes
must be located in a single page address, that is
A14-A6 must be the same for all bytes; if not, the
Page Write instruction is not executed. The page
write can be initiated by any byte write operation.
A page write is composed of successive Write
instructions which have to be sequenced with a
specific period of time between two consecutive
Write instructions, period of time which has to be
smaller than the t
WHWH
value (see Table 12 and
Table 13).
If this period of time exceeds the t
WHWH
value, the
internal programmingcycle will start. Once initiated
the write operation is internally timed until comple-
tion and the status of the Data Polling and the
Toggle Bit functions on DQ7 and DQ6 is controlled
accordingly.
4/21
M28256
Status Register
The devices provide several Write operation status
flags that can be used to minimize the application
write time. These signals are available on the I/O
port bits during programming cycle only.
Data Polling bit (DQ7).
During the internal write
cycle, any attempt to read the last byte written will
produce on DQ7 the complementary value of the
previously latched bit. Once the write cycle is fin-
ished the true logic value appears on DQ7 in the
read cycle.
Toggle bit (DQ6).
The devices offer another way
for determining when the internal write cycle is
completed. During the internal Erase/Write cycle,
DQ6 will toggle from ”0” to ”1” and ”1” to ”0” (the
first read value is ”0”) on subsequent attempts to
read any byte of the memory. When the internal
cycle is completed the toggling will stop and the
data read on DQ7-DQ0 is the addressed memory
byte. The device is now accessible for a new Read
or Write operation.
Page Load TimerStatus bit(DQ5).
Duringa Page
Write instruction, the devices expect to receive the
stream of data with a minimum period of time
between each data byte. This period of time
(t
WHWH
) is defined by the on-chip Page Load timer
which running/overflow status is available on DQ5.
DQ5 Low indicates that the timer is running, DQ5
High indicates the time-out after which the internal
write cycle will start.
Figure 4. Status Bit Assignment
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
DP
TB
PLTS
X
X
X
X
X
DP
= Data Polling
TB
= Toggle Bit
PLTS = Page Load Timer Status
Software Data Protection
The devices offer a software controlled write pro-
tection facility that allows the user to inhibit all write
modes to the device. This can be useful in protect-
ing the memory from inadvertent write cycles that
may occur due to uncontrolledbus conditions.
The devices are shipped as standardin the ”unpro-
tected” state meaning that the memory contents
can be changed as required by the user. After the
Software Data Protection enable algorithm is is-
sued, the device enters the ”Protect Mode” of
operation where no further write commands have
any effect on the memory contents.
The devices remain in this mode until a valid
Software Data Protection (SDP) disable sequence
is received whereby the device reverts to its ”un-
protected” state. The Software Data Protection is
fully non-volatile and is not changed by power
on/off sequences. To enable the Software Data
Protection (SDP) the device requires the user to
write (with a Page Write addressing three specific
data bytes to three specific memorylocations,each
location in a different page) as per Figure 6. Simi-
larly to disable the Software Data Protection the
user has to write specific data bytes into six differ-
ent locations as per Figure 5 (with a Page Write
adressing different bytes in different pages).
This complexseries ensures that the userwill never
enable or disable the Software Data Protection
accidentally.
To write into the devices when SDP is set, the
sequence shown in Figure 6 must be used. This
sequence provides an unlock key to enable the
write action, and at the same time SDP continues
to be set.
An extension to this is where SDP is required to be
set, and data is to be written.
Using the same sequence as above, the data can
be written and SDP is set at the same time, giving
both these actions in the same Write cycle (t
WC
).
5/21
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