PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8430-01
H
IGH
F
REQUENCY
S
YNTHESIZER
F
EATURES
•
Fully integrated PLL
•
Dual differential 3.3V LVPECL output
•
23MHz to 400MHz output frequency
•
±25ps peak-to-peak output jitter
•
Parallel interface for programming counter and output
dividers during power-up
•
Serial 3 wire interface
•
Selectable crystal oscillator interface and LVCMOS refer-
ence input
•
LVCMOS control inputs
•
3.3V supply voltage
•
32 lead low-profile QFP(LQFP), 7mm x 7mm x 1.4mm
package body, 0.8mm package lead pitch
•
0°C to 70°C ambient operating temperature
G
ENERAL
D
ESCRIPTION
The ICS8430-01 is a general purpose, dual
output high frequency synthesizer and a mem-
HiPerClockS™
ber of the HiPerClockS™ family of High Perfor-
mance Clocks Solutions from ICS. The VCO
operates at a frequency range of 280MHz to
400MHz. The output frequency can be programmed using the
serial or parallel interfaces to the configuration logic. With
the output configured to divide the VCO frequency by 2 out-
put frequency steps as small as 0.5MHz can be achieved
using a 16MHz crystal or reference clock.
,&6
B
LOCK
D
IAGRAM
VCO_SEL
XTAL_SEL
REF_IN
XTAL1
OSC
XTAL2
÷
16
0
1
P
IN
A
SSIGNMENT
VCO_SEL
nP_LOAD
XTAL2
M4
M3
M2
M1
M0
32 31 30 29 28 27 26 25
M5
M6
M7
M8
N0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
TEST
VDD
FOUT1
nFOUT1
VDDO
FOUT0
nFOUT0
GND
24
23
22
XTAL1
REF_IN
XTAL_SEL
VDDA
S_LOAD
S_DATA
S_CLOCK
MR
ICS8430-01
21
20
19
18
17
PLL
PHASE DETECTOR
VCO
÷
M
0
÷
N
1
N1
N2
GND
FOUT0
nFOUT0
FOUT1
nFOUT1
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N2
CONFIGURATION
INTERFACE
LOGIC
TEST
32-Lead LQFP
Y Package
Top View
The Advance Information presented herein represents a product currently in design or being considered for design. The noted characteristics are
design targets. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8430-01
www.icst.com
1
REV. A - SEPTEMBER 22, 2000
PRELIMINARY
Integrated
Circuit
Systems, Inc.
F
UNCTIONAL
D
ESCRIPTION
The ICS8430-01 features a fully integrated PLL and therefore requires no external component for setting the loop bandwidth.
A series-resonant , fundamental crystal is used as the input to the on-chip oscillator. The output of the oscillator is divided by
16 prior to the phase detector. With a 16MHz crystal this provides a 1MHz reference frequency. The VCO of the PLL operates
over a range of 280MHz to 400MHz. The output of the loop divider is also applied to the phase detector.
The phase detector and the loop filter force the VCO output frequency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve lock. The output of
the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output
duty cycle.
The programmable features of the ICS8430-01 support two input modes and programmable PLL loop divider and output
divider. The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel
mode the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 through N2 is passed directly to the ripple
counter. On the LOW-to-HIGH transition of the nP_LOAD input the data is latched and the ripple counter remains loaded until
the next LOW transition on nP_LOAD or until a serial event occurs. As a result the M and N bits can be hardwired to set the
ripple counter to a specific default state that will automatically occur during power-up. The TEST output is LOW when operat-
ing in the parallel input mode. The relationship between the VCO frequency, the crystal frequency and the loop divider is
defined as follows:
fxtal x
fVCO =
M
16
The M count and the required values of M0 through M8 are shown in Table4B, Programmable VCO Frequency Function Table.
The frequency out is defined as follows:
fout = fVCO = fxtal x M
N
N
16
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the ripple counter when S_LOAD
transitions from LOW-to-HIGH. The ripple counter divide values are latched on the HIGH-to-LOW transition of S_LOAD. If
S_LOAD is held HIGH data at the S_DATA input is passed directly to the ripple counter on each rising edge of S_CLOCK. The
serial mode can be used to program the M and N bits and test bits T1 and T0. The internal registers T0 and T1 determine the
state of the TEST output as follows:
T1
0
0
1
1
T0
0
1
0
1
TEST Output
LOW
S_Data clocked into register
Output of M divider
CMOS Fout
ICS8430-01
H
IGH
F
REQUENCY
S
YNTHESIZER
S_DATA
S_CLOCK
S_LOAD
M0:M8, N0:N2
nP_LOAD
T1
T0
N2
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
Time
F
IGURE
1. P
ARALLEL
& S
ERIAL
L
OAD
O
PERATIONS
8430-01
www.icst.com
2
REV. A - SEPTEMBER 22, 2000
PRELIMINARY
Integrated
Circuit
Systems, Inc.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
28, 29, 30
31, 32, 1, 2
3, 4
5, 7
6
8, 16
9
10
11, 12
13
14, 15
17
18
19
20
21
22
23
24, 25
26
27
Name
M0, M1, M2
M3, M4, M5, M6
M7, M8
N0, N2
N1
GND
TEST
VDD
FOUT1, nFOUT1
VDDO
FOUT0, nFOUT0
MR
S_CLOCK
S_DATA
S_LOAD
VDDA
XTAL_SEL
REF_IN
XTAL1, XTAL2
nP_LOAD
VCO_SEL
Type
Input
Input
Input
Input
Power
Output
Power
Output
Power
Output
Input
Input
Input
Input
Power
Input
Input
Input
Input
Input
Pulldown
Pullup
Pullup
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pullup
Pulldown
Pullup
Description
M counter/divider inputs. Data latched on LOW-to-HIGH transistion of
nP_LOAD input. LVCMOS / LVTTL interface levels.
Determines output divider value as defined in Table 3 Function Table. LVCMOS
/ LVTTL interface levels.
Power supply ground pin. Connect to ground.
Test output which is ACTIVE in the serial mode of operation. Output driven
LOW in parallel mode. LVCMOS interface levels.
Core power supply pin.
Differential output for the synthesizer. 3.3V LVPECL interface levels.
Output power supply connection. Connect to 3.3V.
Differential output for the synthesizer. 3.3V LVPECL interface levels.
Resets the reference frequency and output dividers. Loads data present at the
M bits into counter. LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register on the
rising edge of S_CLK.
Shift register serial input. Data sampled on the rising edge of S_CLK.
Controls transition of data from shift register into the ripple counter. LVCMOS /
LVTTL interface levels.
Analog power supply pin. Connect to 3.3V.
Selects between cr ystal or reference inputs as the PLL reference source.
LVCMOS / LVTTL interface levels. Selects XTAL inputs when HIGH. Selects
REF_IN when LOW.
Reference clock input. LVCMOS / LVTTL interface levels.
Cr ystal oscillator inputs.
Parallel load input. Determines when data present at M8:M0 is loaded into
ripple counter. LVCMOS / LVTTL interface levels.
Determines whether synthesizer is in PLL or bypass mode. LVCMOS / LVTTL
interface levels.
ICS8430-01
H
IGH
F
REQUENCY
S
YNTHESIZER
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
CIN
RPULLUP
RPULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
51
51
Test Conditions
Minimum
Typical
Maximum
Units
pF
KΩ
KΩ
T
ABLE
3. C
RYSTAL
C
HARACTERISTICS
Parameter
Crystal Cut
Frequency Tolerance
Frequency Stability
Drive Level
Equivalent Series Resistance (ESR)
Shunt Capacitiance
Series Pin Inductance
Aging
Test Conditions
Mode of Oscillation
ppm
ppm
µW
Ω
pF
nH
ppm
Min
Typ
Max
Units
8430-01
www.icst.com
3
REV. A - SEPTEMBER 22, 2000
PRELIMINARY
Integrated
Circuit
Systems, Inc.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage
Inputs
Outputs
Ambient Operating Temperature
Storage Temperature
4.6V
-0.5V to VDD+0.5 V
-0.5V to VDD+0.5V
0°C to 70°C
-65°C to 150°C
ICS8430-01
H
IGH
F
REQUENCY
S
YNTHESIZER
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifica-
tions only and functional operation of the device at these or any conditions beyond those listed in the
DC Electrical Characteristics
or
AC Electrical
Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
T
ABLE
4A. P
ARALLEL
MR
H
L
L
L
L
L
L
nP_LOAD
X
L
↑
H
H
H
H
AND
S
ERIAL
M
ODES
F
UNCTION
T
ABLE
INPUTS
N
X
Data
Data
X
X
X
X
S_LOAD
X
X
X
L
↑
↓
L
S_CLOCK
X
X
X
↑
L
L
X
S_DATA
X
X
X
Data
Data
Data
X
Conditions
Reset. M and N counters reset.
Data on M and N inputs passed directly to ripple
counter. TEST output forced LOW.
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCKt
Contents of the shift register are passed to the ripple
counter.
Ripple counter divide values are latched.
Parallel or serial input do not affect shift registers.
M
X
Data
Data
X
X
X
X
T
ABLE
4B. P
ROGRAMMABLE
VCO F
REQUENCY
F
UNCTION
T
ABLE
VCO Frequency
(MHz)
250
251
252
253
•
•
498
499
500
M Count
250
251
252
253
•
•
498
499
500
256
M8
0
0
0
0
•
•
1
1
1
128
M7
1
1
1
1
•
•
1
1
1
64
M6
1
1
1
1
•
•
1
1
1
32
M5
1
1
1
1
•
•
1
1
1
16
M4
1
1
1
1
•
•
1
1
1
8
M3
1
1
1
1
•
•
0
0
0
4
M2
0
0
1
1
•
•
0
0
1
2
M1
1
1
0
0
•
•
1
1
0
1
M0
0
1
0
1
•
•
0
1
0
T
ABLE
4C. P
ROGRAMMABLE
O
UTPUT
D
IVIDER
F
UNCTION
T
ABLE
Input
N2
0
0
0
0
1
1
1
1
8430-01
N1
0
0
1
1
0
0
1
1
N0
0
1
0
1
0
1
0
1
N Divider
Value
1
1.5
2
3
4
6
8
12
www.icst.com
4
Output Frequency
(MHz)
Min
Max
280
186.66
140
93.33
70
46.66
35
23.33
400
266.66
200
133.33
100
66.66
50
33.33
REV. A - SEPTEMBER 22, 2000
PRELIMINARY
Integrated
Circuit
Systems, Inc.
T
ABLE
5. DC E
LECTRICAL
C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
Symbol
VDD,
VDDA,
VDDO
IDD
VIH
Parameter
Power Supply Voltage
Quiescent Power Supply Current
All except REF_IN, XTAL1, XTAL2
Input High
Voltage
REF_IN
All except REF_IN, XTAL1, XTAL2
VIL
Input Low
Voltage
REF_IN
M0-M6, N0, N2 MR, S_CLOCK,
S_DATA, S_LOAD, REF_IN,
nP_LOAD
M7, M8, N1, XTAL_SEL, VCO_SEL
Input Low
Current
Output High
Voltage;
NOTE 1, 2
Output Low
Voltage;
NOTE 1, 2
Peak-to-Peak
Output Voltage
M0-M6, N0, N2 MR, S_CLOCK,
S_DATA, S_LOAD, REF_IN,
nP_LOAD
M7, M8, N1, XTAL_SEL, VCO_SEL
FOUT0, nFOUT0, FOUT1, nFOUT1
TEST
FOUT0, nFOUT0, FOUT1, nFOUT1
TEST
FOUT0, nFOUT0, FOUT1, nFOUT1
VDDx = 3.465V
3.135
≤
VDDx
≤
3.465V
VDDx = 3.465V
VDDx = 3.135V
3.135
≤
VDDx
≤
3.465V
VDDx = 3.465V
VDDx = 3.135V
VDDx = VIN = 3.465V
VDDx = VIN = 3.465V
VDDx = 3.465V, VIN = 0V
VDDx = 3.465V, VIN = 0V
VDDx = 3.3V
VDDx = 3.135
VDDx = 3.3V
VDDx = 3.135
3.135
≤
VDDx
≤
3.465V
0.6
-150
-5
2.1
2.4
1.6
0.5
2
1.8
1.7
-0.3
-0.3
-0.3
Test Conditions
ICS8430-01
H
IGH
F
REQUENCY
S
YNTHESIZER
TO
70°C
Typical
3.3
Maximum
3.465
110
3.765
3.8
3.4
0.8
1.6
1.5
150
5
Units
V
mA
V
V
V
V
V
V
µA
µA
µA
µA
V
V
V
V
V
Minimum
3.135
IIH
Input High
Current
IIL
VOH
VOL
VPPO
NOTE 1: FOUT0, nFOUT0, FOUT1, nFOUT1 outputs terminated with 5
0Ω
to VDDO-2V.
NOTE 2: These levels are specified for VDDO = 3.3V. Output levels will vary 1:1 with VDDO.
8430-01
www.icst.com
5
REV. A - SEPTEMBER 22, 2000
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