IBM0165165B4M x 1612/10, 3.3V, EDO. IBM0165165P4M x 1612/10, 3.3V, LP, SR, EDO.
IBM0165165B
IBM0165165P
4M x 16 12/10 EDO DRAM
Features
• 4,194,304 word by 16 bit organization
• Single 3.3
±
0.3V power supply
• Extended Data Out (Hyper Page Mode)
• CAS before RAS Refresh
- 4096 cycles/retention Time
• RAS only Refresh
- 4096 cycles/Retention Time
• 64ms Standard Power (SP) Retention Time
• 256ms Low Power (LP) Retention Time
• Hidden Refresh
• Self Refresh (400
µA)
- LP Version Only
• Read-Modify-Write
t
RAC
t
CAC
t
AA
t
RC
t
HPC
• Dual CAS Byte Read/Write
• Performance:
-50
RAS Access Time
CAS Access Time
Column Address Access Time
Cycle Time
Hyper Page Mode Cycle Time
50ns
13ns
25ns
89ns
20ns
-60
60ns
15ns
30ns
104ns
25ns
• Max. Power Dissipation (-60)
- Active: 526mW
- Standby (SP LVCMOS): 3.3mW
- Standby (LP LVCMOS): 0.7mW
• Package: TSOP-54 (500milx875mil)
Description
The IBM0165165B/P is a dynamic RAM organized
4,194,304 words by 16 bits. This device is fabricated
in IBM’s most advanced CMOS silicon gate process
technology. The circuit and process design allow
this DRAM to achieve high performance and low
power dissipation. The IBM0165165B/P operates
with a single 3.3
±
0.3V power supply, and inter-
faces directly with either LVTTL or LVCMOS levels.
The 22 addresses required to access any bit of data
are multiplexed (12 are strobed with RAS, 10 are
strobed with CAS). They are packaged in a 54 pin
plastic TSOP type II (500mil×875mil). The
IBM0165165P parts are low power devices support-
ing Self Refresh and a 256ms retention time.
Currently the 60ns parts are available. The 50ns
parts are under evaluation.
Pin Assignments
(Top View)
Vcc
I/O0
I/O1
I/O2
I/O3
Vcc
I/O4
I/O5
I/O6
I/O7
NC
Vcc
WE
RAS
NC
NC
NC
NC
NC
NC
A0
A1
A2
A3
A4
A5
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
Vss
I/O15
I/O14
I/O13
I/O12
Vss
I/O11
I/O10
I/O9
I/O8
NC
Vss
LCAS
UCAS
OE
NC
NC
NC
NC
NC
A11
A10
A9
A8
A7
A6
Vss
Pin Description
RAS
LCAS / UCAS
WE
A0 - A11
OE
I/O0 - I/O15
V
CC
V
SS
Row Address Strobe
Column Address Strobe
Read/write Input
Address Inputs
Output Enable
Data Input/output
Power (+3.3V)
Ground
27H6253
SA14-4239-01
Revised 4/96
©IBM Corporation, 1996. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 30
IBM0165165B
IBM0165165P
4M x 16 12/10 EDO DRAM
Ordering Information
Part Number
IBM0165165BT5B-50
IBM0165165BT5B-60
IBM0165165PT5B-50
IBM0165165PT5B-60
Power
SP
SP
LP
LP
Self Refresh
No
No
Yes
Yes
Power Supply
3.3V
3.3V
3.3V
3.3V
Speed
50ns
60ns
50ns
60ns
Package
500mil TSOP 54
500mil TSOP 54
500mil TSOP 54
500mil TSOP 54
Notes
1
1
1
1
1. SP = Standard Power version (IBM0165165B); LP = Low Power version (IBM0165165P)
Block Diagram
I/O1 I/O3 I/O5
I/O7
I/O2
I/O4
I/O6
I/O9 I/O11 I/O13 I/O15
I/O8 I/O10 I/O12 I/O14
Vcc
Vss
I/O0
8
OE
Lower Data I/O Buffer
And
OE
8
Upper Data I/O Buffer
WE
8
WE
And
8
LCAS
UCAS
Or
No. 2 Clock
Generator
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
10
Column
Address
Buffer (9)
10
Column Decoder
Sense Amp and I/O Gate
16
Refresh
Controller
1024x16
Row Decoder
Refresh
Counter (13)
12
12
RAS
Row
Address
Buffer (13)
No. 1 Clock
Generator
Memory
4096
Array
4096 x 1024 x 16
12
©IBM Corporation, 1996. All rights reserved.
Use is further subject to the provisions at the end of this document.
27H6253
SA14-4239-01
Revised 4/96
Page 2 of 30
IBM0165165B
IBM0165165P
4M x 16 12/10 EDO DRAM
Truth Table
Function
Standby
Read: Word
Read: Lower Byte
Read: Upper Byte
Write: Word
Early-Write
Write: Lower Byte
Early-Write
Write: Upper Byte
Early-Write
Read-Modify-Write
EDO (Hyper Page) Mode
Read
EDO (Hyper Page) Mode
Write
EDO (Hyper Page) Mode
Read-Modify-Write
RAS-Only Refresh
CAS-Before-RAS Refresh
Read
Hidden Refresh
Write
Self Refresh (LP version only)
L→H→L
H→L
L
L
L
L
H
H
X
X
Row
X
Col
X
Data In
High Impedance
1st Cycle
2nd Cycle
1st Cycle
2nd Cycle
1st Cycle
2nd Cycle
RAS
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H→L
L→H→L
LCAS
H→X
L
L
H
L
L
H
L
H→L
H→L
H→L
H→L
H→L
H→L
H
L
L
UCAS
H→X
L
H
L
L
H
L
L
H→L
H→L
H→L
H→L
H→L
H→L
H
L
L
WE
X
H
H
H
L
L
L
H→L
H
H
L
L
H→L
H→L
X
H
H
OE
X
L
L
L
X
X
X
L→H
L
L
X
X
L→H
L→H
X
X
L
Row
Column
Address Address
X
Row
Row
Row
Row
Row
Row
Row
Row
N/A
Row
N/A
Row
N/A
Row
X
Row
X
Col
Col
Col
Col
Col
Col
Col
Col
Col
Col
Col
Col
Col
N/A
N/A
Col
I/O0 - I/O15
High Impedance
Data Out
Lower Byte: Data Out
Upper Byte: High-Z
Lower Byte: High-Z
Upper Byte: Data Out
Data In
Lower Byte: Data In
Upper Byte: High-Z
Lower Byte: High-Z
Upper Byte: Data In
Data Out, Data In
Data Out
Data Out
Data In
Data In
Data Out, Data In
Data Out, Data In
High Impedance
High Impedance
Data Out
27H6253
SA14-4239-01
Revised 4/96
©IBM Corporation, 1996. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 3 of 30
IBM0165165B
IBM0165165P
4M x 16 12/10 EDO DRAM
Absolute Maximum Ratings
Symbol
V
CC
V
IN
V
OUT
T
OPR
T
STG
P
D
I
OUT
Parameter
Power Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Storage Temperature
Power Dissipation
Short Circuit Output Current
Rating
-0.5 to 4.6
-0.5 to min (V
CC
+0.5, 4.6)
-0.5 to min (V
CC
+0.5, 4.6)
0 to +70
-55 to +150
1.0
50
Units
V
V
V
°C
°C
W
mA
Notes
1
1
1
1
1
1
1
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli-
ability.
Recommended DC Operating Conditions
Symbol
V
CC
V
IH
V
IL
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Min.
3.0
2.0
-0.3
(T
A
=0 to 70°C)
Typ.
3.3
—
—
Max.
3.6
V
CC
+ 0.3
0.8
Units
V
V
V
Notes
1
1,2
1,2
1. All voltages referenced to V
SS
.
2. V
IH
may overshoot to V
CC
+ 2.0V for pulse widths of
≤
4.0ns with 3.3 Volt. V
IL
may undershoot to -2.0V for pulse widths
≤
4.0ns
with 3.3 Volt. Pulse widths measured at 50% points with amplitude measured peak to DC reference
Capacitance
(T
A
=0 to +70°C, V
CC
=3.3
±
0.3V, f=1MHz)
Symbol
C
I1
C
I2
C
I3
Parameter
Input Capacitance (A0 - A11)
Input Capacitance (RAS, LCAS, UCAS, WE, OE)
Data I/O Capacitance (I/O0 - I/15)
Min.
—
—
—
Max.
5
7
7
Units
pF
pF
pF
Notes
©IBM Corporation, 1996. All rights reserved.
Use is further subject to the provisions at the end of this document.
27H6253
SA14-4239-01
Revised 4/96
Page 4 of 30
IBM0165165B
IBM0165165P
4M x 16 12/10 EDO DRAM
DC Electrical Characteristics
(T
A
= 0 to +70°C, V
CC
= 3.3
±
0.3V)
Symbol
I
CC1
Parameter
Operating Current
Average Power Supply Operating Current
(RAS, CAS, Address Cycling: t
RC
= t
RC
min)
Standby Current (LVTTL)
Power Supply Standby Current
(RAS = CAS = V
IH
)
RAS Only Refresh Current
Average Power Supply Current, RAS Only Mode
(RAS Cycling, CAS = V
IH
: t
RC
= t
RC
min)
EDO (Hyper Page) Mode Current
Average Power Supply Current, Hyper Page Mode
(RAS = V
IL
, CAS, Address Cycling: t
PC
= t
PC
min)
Standby Current (LVCMOS)- Low Power
Power Supply Standby Current
(RAS = CAS = V
CC
- 0.2V)
Standby Current (LVCMOS)- Standard Power
Power Supply Standby Current
(RAS = CAS = V
CC
- 0.2V)
CAS Before RAS Refresh Current
Average Power Supply Current, CAS Before RAS Mode
(RAS, CAS, Cycling: t
RC
= t
RC
min)
Self Refresh Current (LP version only)
Average Power Supply Current during Self Refresh
CBR cycle with RAS
≥
t
RASS
(min); CAS held low;
WE = V
CC
- 0.2V; Addresses and D
IN
= V
CC
- 0.2V or 0.2V.
Input Leakage Current
Input Leakage Current, any input
(0.0
≥
V
IN
≥
V
CC
), All Other Pins Not Under Test = 0V
Output Leakage Current
(D
OUT
is disabled, 0.0
≥
V
OUT
≥
V
CC
)
Output High Level (LVTTL)
Output “H” Level Voltage (I
OUT
= -2mA)
Output Low Level (LVTTL)
Output “L” Level Voltage (I
OUT
= +2mA)
Output High Level (LVCMOS)
Output “H” Level Voltage (I
OUT
= -100µA)
Output Low Level (LVCMOS)
Output “L” Level Voltage (I
OUT
= +100µA)
-50
-60
-50
-60
-50
-60
-50
-60
Min.
—
—
—
Max.
175
145
2
145
Units
mA
Notes
1, 2, 3
I
CC2
mA
I
CC3
mA
1, 3
—
—
—
—
120
150
120
200
µA
mA
1, 2, 3
I
CC4
I
CC5
—
—
—
—
1
150
125
400
mA
I
CC6
mA
1, 2
I
CC7
µA
I
I(L)
I
O(L)
V
OH
V
OL
V
OH
V
OL
1.
2.
3.
4.
-2
-2
2.4
—
V
CC
- 0.2
—
+2
+2
—
0.4
—
0.2
µA
µA
V
V
V
V
4
4
I
CC1
, I
CC3
, I
CC4
, I
CC6
depend on cycle rate.
I
CC1
, I
CC4
depend on output loading. Specified values are obtained with the output open.
Column address can be changed once or less while RAS =V
IL
and CAS =V
IH
.
V
OL
(LVCMOS) and V
OH
(LVCMOS) levels are not intended for use as timing reference levels. LVCMOS levels are the quiescent
state of a low impedance output driver, under the specified load condition.
27H6253
SA14-4239-01
Revised 4/96
©IBM Corporation, 1996. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 5 of 30
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