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MSC8156: DescriptionHigh-performance six-core DSP; File Size1MB，69 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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MSC8156 Overview

High-performance six-core DSP

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Freescale Semiconductor

Data Sheet

Document Number: MSC8156

Rev. 6, 7/2013

MSC8156

Six-Core Digital Signal

Processor

FC-PBGA–783

29 mm

⋅

29 mm

• Six StarCore SC3850 DSP subsystems, each with an SC3850

DSP core, 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache,

unified 512 Kbyte L2 cache configurable as M2 memory in

64 Kbyte increments, memory management unit (MMU),

extended programmable interrupt controller (EPIC), two

general-purpose 32-bit timers, debug and profiling support,

low-power Wait, Stop, and power-down processing modes, and

ECC/EDC support.

• Chip-level arbitration and switching system (CLASS) that

provides full fabric non-blocking arbitration between the cores

and other initiators and the M2 memory, shared M3 memory,

DDR SRAM controllers, device configuration control and status

registers, MAPLE-B, and other targets.

• 1056 Kbyte 128-bit wide M3 memory, 1024 Kbytes of which can

be turned off to save power.

• 96 Kbyte boot ROM.

• Three input clocks (one global and two differential).

• Five PLLs (three global and two Serial RapidIO PLLs).

• Multi-Accelerator Platform Engine for Baseband (MAPLE-B)

with a programmable system interface, Turbo decoding, Viterbi

decoding, and FFT/iFFT and DFT/iDFT processing. MAPLE-B

can be disabled when not required to reduce overall power

consumption.

• Two DDR controllers with up to a 400 MHz clock (800 MHz data

rate), 64/32 bit data bus, supporting up to a total 2 Gbyte in up to

four banks (two per controller) and support for DDR2 and DDR3.

• DMA controller with 32 unidirectional channels supporting 16

memory-to-memory channels with up to 1024 buffer descriptors

per channel, and programmable priority, buffer, and multiplexing

configuration. It is optimized for DDR SDRAM.

• Up to four independent TDM modules with programmable word

size (2, 4, 8, or 16-bit), hardware-base A-law/μ-law conversion,

up to 62.5 Mbps data rate for each TDM link, and with glueless

interface to E1 or T1 framers that can interface with

H-MVIP/H.110 devices, TSI, and codecs such as AC-97.

• High-speed serial interface that supports two Serial RapidIO

interfaces, one PCI Express interface, and two SGMII interfaces

(multiplexed). The Serial RapidIO interfaces support 1x/4x

operation up to 3.125 Gbaud with a single messaging unit and two

DMA units. The PCI Express controller supports 32- and 64-bit

addressing, x4, x2, and x1 link.

• QUICC Engine technology subsystem with dual RISC

processors, 48 Kbyte multi-master RAM, 48 Kbyte instruction

RAM, supporting two communication controllers for two Gigabit

Ethernet interfaces (RGMII or SGMII), to offload scheduling

tasks from the DSP cores, and an SPI.

• I/O Interrupt Concentrator consolidates all chip maskable

interrupt and non-maskable interrupt sources and routes then to

INT_OUT, NMI_OUT, and the cores.

• UART that permits full-duplex operation with a bit rate of up to

6.25 Mbps.

• Two general-purpose 32-bit timers for RTOS support per SC3850

core, four timer modules with four 16-bit fully programmable

timers, and eight software watchdog timers (SWT).

• Eight programmable hardware semaphores.

• Up to 32 virtual interrupts and a virtual NMI asserted by simple

write access.

• I

C interface.

• Up to 32 GPIO ports, sixteen of which can be configured as

external interrupts.

• Boot interface options include Ethernet, Serial RapidIO interface,

C, and SPI.

• Supports standard JTAG interface

• Low power CMOS design, with low-power standby and

power-down modes, and optimized power-management circuitry.

• 45 nm SOI CMOS technology.

Table of Contents

Pin Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

1.1 FC-PBGA Ball Layout Diagram . . . . . . . . . . . . . . . . . . . .4

1.2 Signal List By Ball Location. . . . . . . . . . . . . . . . . . . . . . .5

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

2.2 Recommended Operating Conditions . . . . . . . . . . . . . .25

2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .25

2.4 CLKIN Requirements . . . . . . . . . . . . . . . . . . . . . . . . . .26

2.5 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .26

2.6 AC Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . .37

Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . .55

3.1 Power Supply Ramp-Up Sequence. . . . . . . . . . . . . . . .55

3.2 PLL Power Supply Design Considerations . . . . . . . . . .58

3.3 Clock and Timing Signal Board Layout Considerations 59

3.4 SGMII AC-Coupled Serial Link Connection Example . .59

3.5 Connectivity Guidelines . . . . . . . . . . . . . . . . . . . . . . . .60

3.6 Guide to Selecting Connections for Remote Power

Supply Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Figure 11.DDR2 and DDR3 SDRAM Interface Input Timing

Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 12.MCK to MDQS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 13.DDR SDRAM Output Timing . . . . . . . . . . . . . . . . . . . . . 40

Figure 14.DDR2 and DDR3 Controller Bus AC Test Load. . . . . . . 40

Figure 15.DDR2 and DDR3 SDRAM Differential Timing

Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 16.Differential Measurement Points for Rise and Fall Time 42

Figure 17.Single-Ended Measurement Points for Rise and Fall Time

Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 18.Single Frequency Sinusoidal Jitter Limits . . . . . . . . . . . 45

Figure 19.SGMII AC Test/Measurement Load . . . . . . . . . . . . . . . . 46

Figure 20.TDM Receive Signals . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 21.TDM Transmit Signals . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 22.TDM AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 23.Timer AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 24.MII Management Interface Timing . . . . . . . . . . . . . . . . . 50

Figure 25.RGMII AC Timing and Multiplexing . . . . . . . . . . . . . . . . 51

Figure 26.SPI AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 27.SPI AC Timing in Slave Mode (External Clock) . . . . . . . 52

Figure 28.SPI AC Timing in Master Mode (Internal Clock) . . . . . . 52

Figure 29.Test Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 30.Boundary Scan (JTAG) Timing . . . . . . . . . . . . . . . . . . . 54

Figure 31.Test Access Port Timing . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 32.TRST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 33.Supply Ramp-Up Sequence with V

Ramping Before

DDIO

and CLKIN Starting With V

DDIO

. . . . . . . . . . . . . 55

Figure 34.Supply Ramp-Up Sequence . . . . . . . . . . . . . . . . . . . . . 57

Figure 35.Reset Connection in Functional Application . . . . . . . . . 57

Figure 36.Reset Connection in Debugger Application . . . . . . . . . . 57

Figure 37.PLL Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 38.SerDes PLL Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 39.4-Wire AC-Coupled SGMII Serial Link Connection

Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 40.MSC8156 Mechanical Information, 783-ball FC-PBGA

Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

List of Figures

MSC8156 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 3

StarCore SC3850 DSP Subsystem Block Diagram . . . . 3

MSC8156 FC-PBGA Package, Top View . . . . . . . . . . . . 4

Differential Voltage Definitions for Transmitter or

Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 5. Receiver of SerDes Reference Clocks . . . . . . . . . . . . . 30

Figure 6. SerDes Transmitter and Receiver Reference Circuits. . 31

Figure 7. Differential Reference Clock Input DC Requirements

(External DC-Coupled) . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 8. Differential Reference Clock Input DC Requirements

(External AC-Coupled) . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 9. Single-Ended Reference Clock Input DC Requirements 33

Figure 10.SGMII Transmitter DC Measurement Circuit. . . . . . . . . 35

Figure 1.

Figure 2.

Figure 3.

Figure 4.

MSC8156 Six-Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

MSC8156 Related Products

	MSC8156	MSC8156TAG1000B	MSC8156ETAG1000B	MSC8156SAG1000B	MSC8156ESAG1000B
Description	High-performance six-core DSP	Digital Signal Processors u0026 Controllers - DSP, DSC BL Digital Networking	Digital Signal Processors u0026 Controllers - DSP, DSC BL Digital Networking	Digital Signal Processors & Controllers - DSP, DSC StarCore DSP, 6x 1GHz SC3850 cores, MAPLE-B accelerator, DDR2/3, SRIO, PCIe, QE, GbE, 0-105C	Digital Signal Processors & Controllers - DSP, DSC MSC8156ESAG1000B/BGA783///STANDARD MARKING * TRAY
Product Category	-	-	Digital Signal Processors & Controllers - DSP, DSC	Digital Signal Processors & Controllers - DSP, DSC	Digital Signal Processors & Controllers - DSP, DSC
Manufacturer	-	-	NXP	NXP	NXP
Product	-	-	DSPs	DSPs	DSPs
Core	-	-	SC3850	SC3850	SC3850
Maximum Clock Frequency	-	-	1 GHz	1 GHz	1 GHz
L1 Cache Instruction Memory	-	-	32 kB	32 kB	32 kB
L1 Cache Data Memory	-	-	32 kB	32 kB	32 kB
Data RAM Size	-	-	1.03 MB	1.03 MB	1.03 MB
Operating Supply Voltage	-	-	1 V	1 V	1 V
Maximum Operating Temperature	-	-	+ 105 C	+ 105 C	+ 105 C
Mounting Style	-	-	SMD/SMT	SMD/SMT	SMD/SMT
Package / Case	-	-	FCBGA-783	FCBGA-783	FCBGA-783
Data Bus Width	-	-	32 bit, 64 bit	32 bit, 64 bit	32 bit, 64 bit
I/O Voltage	-	-	1 V, 2.5 V	1 V, 2.5 V	1 V, 2.5 V
Interface Type	-	-	Ethernet, I2C, SPI	Ethernet, I2C, SPI	Ethernet, I2C, SPI
L2 Cache Instruction / Data Memory	-	-	512 kB	512 kB	512 kB
Minimum Operating Temperature	-	-	- 40 C	0 C	0 C
Number of Cores	-	-	6 Core	6 Core	6 Core
Number of Timers/Counters	-	-	18 Timer	18 Timer	18 Timer
Processor Series	-	-	StarCore	StarCore	StarCore
Supply Voltage - Max	-	-	1.05 V	1.05 V	1.05 V
Supply Voltage - Min	-	-	0.97 V	0.97 V	0.97 V
Watchdog Timers	-	-	Watchdog Timer	Watchdog Timer	Watchdog Timer
Unit Weight	-	-	0.393047 oz	0.393047 oz	0.393047 oz

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