Freescale Semiconductor
Technical Data
Document Number: MPC8272EC
Rev. 3, 09/2011
MPC8272
PowerQUICC II Family
Hardware Specifications
This document contains detailed information about power
considerations, DC/AC electrical characteristics, and AC
timing specifications for .13µm (HiP7) members of the
PowerQUICC II family of integrated communications
processors—the MPC8272, the MPC8248, the MPC8271,
and the MPC8247. They include on a single chip a 32-bit
Power Architecture® core that incorporates memory
management units (MMUs) and instruction and data caches
and that implements the Power Architecture instruction set;
a modified communications processor module (CPM); and
an integrated security engine (SEC) for encryption (the
MPC8272 and the MPC8248 only).
All four devices are collectively referred to throughout this
hardware specification as “the MPC8272” unless otherwise
noted.
Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 7
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . 9
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . 14
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . 18
Clock Configuration Modes . . . . . . . . . . . . . . . . . . . 27
Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 56
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 58
Document Revision History . . . . . . . . . . . . . . . . . . . 58
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© 2011 Freescale Semiconductor, Inc. All rights reserved.
Overview
1
Overview
Table 1. MPC8272 PowerQUICC II Family Functionality
SoCs
Functionality
Package
1
Serial communications controllers (SCCs)
QUICC multi-channel controller (QMC)
Fast communication controllers (FCCs)
I-Cache (Kbyte)
D-Cache (Kbyte)
Ethernet (10/100)
UTOPIA II Ports
Multi-channel controllers (MCCs)
PCI bridge
Transmission convergence (TC) layer
Inverse multiplexing for ATM (IMA)
Universal serial bus (USB) 2.0 full/low rate
Security engine (SEC)
1
This table shows the functionality supported by each SoC in the MPC8272 family.
MPC8272
MPC8248
MPC8271
MPC8247
516 PBGA
3
Yes
2
16
16
2
1
0
Yes
—
—
1
Yes
3
Yes
2
16
16
2
0
0
Yes
—
—
1
Yes
3
Yes
2
16
16
2
1
0
Yes
—
—
1
—
3
Yes
2
16
16
2
0
0
Yes
—
—
1
—
See
Table 2.
Devices in the MPC8272 family are available in two packages—the VR or ZQ package—as shown in .
For package ordering information, see
Section 10, “Ordering Information.”
Table 2. MPC8272 PowerQUICC II Device Packages
Code
(Package)
VR
(516 PBGA—Lead free)
MPC8272VR
MPC8248VR
Device
MPC8271VR
MPC8247VR
MPC8271ZQ
MPC8247ZQ
ZQ
(516 PBGA—Lead spheres)
MPC8272ZQ
MPC8248ZQ
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
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Freescale Semiconductor
Overview
This figure shows the block diagram of the SoC.
16 KB
I-Cache
Security (SEC)1
I-MMU
G2_LE Core
System Interface Unit
(SIU)
16 KB
D-Cache
D-MMU
Bus Interface Unit
60x-to-PCI
Bridge
Memory Controller
Communication Processor Module (CPM)
Timers
Parallel I/O
Baud Rate
Generators
4 KB
Interrupt
Instruction
Controller
RAM
16 KB
Data
RAM
Clock Counter
Serial
DMA
Virtual
IDMAs
System Functions
60x Bus
PCI Bus
32 bits, up to 66 MHz
32-bit RISC Microcontroller
and Program ROM
FCC1
FCC2
SCC1
SCC3
SCC4
SMC1
SMC2
SPI
I
2
C
USB 2.0
Time Slot Assigner
Serial interface
Serial Interface
2 TDM Ports
2 MII/RMII
Ports
1 8-bit Utopia
Port2
Non-Multiplexed
I/O
Notes:
1 MPC8272/8248 only
2 MPC8272/8271 only
Figure 1. SoC Block Diagram
1.1
Features
The major features of the SoC are as follows:
• Dual-issue integer (G2_LE) core
— A core version of the MPC603e microprocessor
— System core microprocessor supporting frequencies of 266–400 MHz
— Separate 16 KB data and instruction caches:
– Four-way set associative
– Physically addressed
– LRU replacement algorithm
— Power Architecture®-compliant memory management unit (MMU)
— Common on-chip processor (COP) test interface
— Supports bus snooping for cache coherency
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
Freescale Semiconductor
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Overview
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— Floating-point unit (FPU) supports floating-point arithmetic
— Support for cache locking
Low-power consumption
Separate power supply for internal logic (1.5 V) and for I/O (3.3 V)
Separate PLLs for G2_LE core and for the communications processor module (CPM)
— G2_LE core and CPM can run at different frequencies for power/performance optimization
— Internal core/bus clock multiplier that provides ratios 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1, 5:1,
5.5:1, 6:1, 7:1, 8:1
— Internal CPM/bus clock multiplier that provides ratios 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1, 8:1
ratios
64-bit data and 32-bit address 60x bus
— Bus supports multiple master designs—up to two external masters
— Supports single transfers and burst transfers
— 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
60x-to-PCI bridge
— Programmable host bridge and agent
— 32-bit data bus, 66 MHz, 3.3 V
— Synchronous and asynchronous 60x and PCI clock modes
— All internal address space available to external PCI host
— DMA for memory block transfers
– PCI-to-60x address remapping
System interface unit (SIU)
— Clock synthesizer
— Reset controller
— Real-time clock (RTC) register
— Periodic interrupt timer
— Hardware bus monitor and software watchdog timer
— IEEE 1149.1 JTAG test access port
Eight bank memory controller
— Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash, and other
user-definable peripherals
— Byte write enables
— 32-bit address decodes with programmable bank size
— Three user-programmable machines, general-purpose chip-select machine, and page mode
pipeline SDRAM machine
— Byte selects for 64-bit bus width (60x)
— Dedicated interface logic for SDRAM
Disable CPU mode
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
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Freescale Semiconductor
Overview
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•
•
Integrated security engine (SEC) (MPC8272 and MPC8248 only)
— Supports DES, 3DES, MD-5, SHA-1, AES, PKEU, RNG and RC-4 encryption algorithms
in hardware
Communications processor module (CPM)
— Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support
for communications peripherals
— Interfaces to G2_LE core through on-chip dual-port RAM and DMA controller. (Dual-port
RAM size is 16 KB plus 4 KB dedicated instruction RAM.)
— Microcode tracing capabilities
— Eight CPM trap registers
Universal serial bus (USB) controller
— Supports USB 2.0 full/low rate compatible
— USB host mode
– Supports control, bulk, interrupt, and isochronous data transfers
– CRC16 generation and checking
– NRZI encoding/decoding with bit stuffing
– Supports both 12- and 1.5-Mbps data rates (automatic generation of preamble token and
data rate configuration). Note that low-speed operation requires an external hub.
– Flexible data buffers with multiple buffers per frame
– Supports local loopback mode for diagnostics (12 Mbps only)
— Supports USB slave mode
– Four independent endpoints support control, bulk, interrupt, and isochronous data transfers
– CRC16 generation and checking
– CRC5 checking
– NRZI encoding/decoding with bit stuffing
– 12- or 1.5-Mbps data rate
– Flexible data buffers with multiple buffers per frame
– Automatic retransmission upon transmit error
— Serial DMA channels for receive and transmit on all serial channels
— Parallel I/O registers with open-drain and interrupt capability
— Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers
— Two fast communication controllers (FCCs) supporting the following protocols:
– 10-/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent
interface (MII)
– Transparent
– HDLC—up to T3 rates (clear channel)
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
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