HD74ALVCH16832
1-to-4 Address Register / Driver with 3-state Outputs
REJ03D0030-0400Z
(Previous ADE-205-214B(Z))
Rev.4.00
Oct.02.2003
Description
This 1-bit to 4-bit address register / driver is designed for 2.3 V to 3.6 V V
CC
operation.
The device is ideal for use in applications in which a single address bus is driving four separate memory
locations. The HD74ALVCH16832 can be used as a buffer or a register, depending on the logic level of
the select (SEL) input.
When
SEL
is a logic high, the device is in the buffer mode. The outputs follow the inputs and are
controlled by the two output enable (OE) inputs. Each
OE
controls two groups of seven outputs.
When
SEL
is a logic low, the device is in the register mode. The register is an edge triggered D-type flip
flop. On the positive transition of the clock (CLK) input, data at the A inputs is stored in the internal
registers.
OE
controls operate the same as in the buffer mode.
When
OE
is a logic low, the outputs are in a normal logic state (high or low logic level). When
OE
is a
logic high, the outputs are in the high impedance state.
Neither
SEL
nor
OE
affect the internal operation of the flip flops. Old data can be retained or new data can
be entered while the outputs are in the high impedance state.
To ensure the high impedance state during power up or power down,
OE
should be tied to V
CC
through a
pull up resistor; the minimum value of the resistor is determined by the current sinking capability of the
driver.
Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Features
•
•
•
•
•
V
CC
= 2.3 V to 3.6 V
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25°C)
Typical V
OH
undershoot > 2.0 V (@V
CC
= 3.3 V, Ta = 25°C)
High output current ±24 mA (@V
CC
= 3.0 V)
Bus hold on data inputs eliminates the need for external pull up / pull down resistors
Rev.4.00, Oct.02.2003, page 1 of 11
HD74ALVCH16832
Absolute Maximum Ratings
Item
Supply voltage
Input voltage
*1
Output voltage
*1, 2
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
or I
GND
P
T
T
stg
Ratings
–0.5 to 4.6
–0.5 to 4.6
–0.5 to V
CC
+0.5
–50
±50
±50
±100
1
–65 to 150
Unit
V
V
V
mA
mA
mA
mA
W
°C
Conditions
Input clamp current
Output clamp current
Continuous output current
V
CC
, GND current / pin
Maximum power dissipation
*3
at Ta = 55°C (in still air)
Storage temperature
Notes:
V
I
< 0
V
O
< 0 or V
O
> V
CC
V
O
= 0 to V
CC
TSSOP
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage
to the device. These are stress ratings only, and functional operation of the device at these or
any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp
current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C
and a board trace length of 750 mils.
Recommended Operating Conditions
Item
Supply voltage
Input voltage
Output voltage
High level output current
Symbol
V
CC
V
I
V
O
I
OH
Min
2.3
0
0
—
—
—
Low level output current
I
OL
—
—
—
Input transition rise or fall rate
Operating temperature
∆t
/
∆v
T
a
0
–40
Max
3.6
V
CC
V
CC
–12
–12
–24
12
12
24
10
85
ns / V
°C
mA
Unit
V
V
V
mA
V
CC
= 2.3 V
V
CC
= 2.7 V
V
CC
= 3.0 V
V
CC
= 2.3 V
V
CC
= 2.7 V
V
CC
= 3.0 V
Conditions
Note: Unused control inputs must be held high or low to prevent them from floating.
Rev.4.00, Oct.02.2003, page 4 of 11
Embedded System
京公网安备 11010802033920号
EEWORLD
