TDA8757A
Triple 8-bit ADC 205 Msps
Rev. 01 — 22 March 2002
Preliminary data
1. General description
The TDA8757A is a triple 8-bit ADC for the digitizing of large bandwidth RGB/YUV
signals at a sampling rate up to 205 Msps.
The IC supports display resolutions up to 1600
×
1200 (UXGA) at 75 Hz.
The IC also includes a PLL that can be locked to the horizontal line frequency and
generates the ADC clock. The PLL jitter is minimized for high resolution PC graphics
applications. An external clock signal can also be used to clock the ADC.
The outputs are available either on one port up to 110 Msps or on two ports up to
205 Msps. The operating mode is selectable with the serial interface for either
I
2
C-bus or 3-wire serial bus (3W-bus) operation.
The clamp level, the gain and the other settings are controllable through the serial
interface.
2. Features
s
Triple 8-bit ADC
s
Sampling rate up to 205 Msps
s
IC controllable by a serial interface which can be I
2
C-bus or 3W-bus, selected by a
TTL input pin
s
Three clamps for programming a clamping code from
−63.5
to +64 in steps of
1
⁄
LSB (RGB) and from +120 to +136 in steps of
1
⁄
LSB (YUV)
2
2
s
Three controllable amplifiers: gain controlled through the serial interface to
produce a full-scale resolution of
1
⁄
2
LSB peak-to-peak
s
Amplifier bandwidth of 250 MHz
s
Low gain variation with temperature
s
PLL controllable with the serial interface to generate the ADC clock which can be
locked to any line frequency of 15 to 150 kHz
s
Integrated PLL divider
s
Programmable phase clock adjustment cells
s
Internal voltage regulators
s
TTL compatible digital inputs and outputs
s
Outputs on one port or demultiplexed on two ports; selectable with the serial
interface
s
Chip enable high-impedance ADC output
s
Power-down mode
s
1.7 W power dissipation
s
Sync on green extractor.
Philips Semiconductors
TDA8757A
Triple 8-bit ADC 205 Msps
3. Applications
s
s
s
s
RGB/YUV high-speed digitizing
LCD panels drive
LCD projection systems
VGA to UXGA (1600
×
1200 at 75 Hz) modes.
4. Quick reference data
Table 1:
Symbol
V
CCA
V
DDD
V
CCD
V
CCO
V
CCA(PLL)
V
CCO(PLL)
I
CCA
I
DDD
I
CCD
I
CCO
I
CCA(PLL)
f
clk
f
ref(PLL)
f
PLL
INL
Quick reference data
Parameter
analog supply voltage for PLL
and the RGB channels
logic supply voltage for I
2
C-bus
and 3W-bus
digital supply voltage
output stages supply voltage
for PLL and the RGB channels
analog PLL supply voltage
output PLL supply voltage
analog supply current for the
RGB channels
logic supply current for I
2
C-bus
and 3W-bus
digital supply current
output stages supply current
analog PLL supply current
clock frequency
PLL reference clock frequency
output clock frequency range
DC integral non-linearity
from analog input to
digital output; full-scale;
sine wave input;
f
clk
= 205 MHz
from analog input to
digital output; full-scale;
sine wave input;
f
clk
= 205 MHz
normal (Dmx = 0)
demultiplexed (Dmx = 1)
Conditions
Min
4.75
4.75
4.75
4.75
4.75
4.75
−
−
−
−
−
−
−
15
12
−
Typ
5.0
5.0
5.0
5.0
5.0
5.0
135
1
95
80
34
−
−
−
−
±0.5
Max
5.25
5.25
5.25
5.25
5.25
5.25
−
−
−
−
−
110
205
150
205
±1.5
Unit
V
V
V
V
V
V
mA
mA
mA
mA
mA
MHz
MHz
kHz
MHz
LSB
DNL
DC differential non-linearity
−
±0.4
±1
LSB
∆G
amp
/∆T
B
t
set(ADC+AGC)
amplifier gain stability variation V
ref
= 2.5 V with
with temperature
100 ppm/°C maximum
amplifier bandwidth
settling time of the block
ADC + AGC
−3
dB; T
amb
= 25
°C
input signal settling
time <1 ns; settling to
1%; f
i
= 85 MHz
−
250
−
325
−
4
−
−
−
ppm/°C
MHz
ns
9397 750 09549
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Preliminary data
Rev. 01 — 22 March 2002
2 of 37
PCB Design
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