64K x 16 Bank-Switchable Dual-Ported SRAM Architecture
– Four independent 16K x 16 banks
– 1 Megabit of memory on chip
Fast asynchronous address-to-data access time: 15ns
User-controlled input pins included for bank selects
Independent port controls with asynchronous address & data
busses
Four 16-bit mailboxes available to each port for inter-
processor communications; interrupt option
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
Interrupt flags with programmable masking
Dual Chip Enables allow for depth expansion without
external logic
UB
and
LB
are available for x8 or x16 bus matching
LVTTL-compatible, single 3.3V (±5%) power supply
Available in a 100-pin Thin Quad Flatpack (14mm x 14mm)
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Functional Block Diagram
MUX
R/W
L
CE
0L
CE
1L
UB
L
LB
L
OE
L
16Kx16
MEMORY
ARRAY
(BANK 0)
MUX
I/O
8L-15L
I/O
0L-7L
I/O
CONTROL
MUX
16Kx16
MEMORY
ARRAY
(BANK 1)
MUX
I/O
CONTROL
I/O
8R-15R
I/O
0R-7R
R/W
R
CE
0R
CE
1R
UB
R
LB
R
OE
R
CONTROL
LOGIC
CONTROL
LOGIC
A
13L
A
0L(1)
ADDRESS
DECODE
ADDRESS
DECODE
A
13R
A
0R(1)
BA
1L
BA
0L
BANK
DECODE
MUX
16Kx16
MEMORY
ARRAY
(BANK 3)
MUX
BANK
DECODE
BA
1R
BA
0R
BKSEL
3(2)
BKSEL
0(2)
BANK
SELECT
A
5L (1)
A
0L (1)
LB
L
/UB
L
OE
L
R/W
L
CE
L
MAILBOX
INTERRUPT
LOGIC
A
5R(1)
A
0R(1)
LB
R
/UB
R
OE
R
R/W
R
CE
R
MBSEL
L
INT
L
MBSEL
R
INT
R
4077 drw 01
NOTES:
1. The first six address pins for each port serve dual functions. When
MBSEL
= V
IH
, the pins serve as memory address inputs. When
MBSEL
= V
IL
, the pins serve as mailbox
address inputs.
2. Each bank has an input pin assigned that allows the user to toggle the assignment of that bank between the two ports. Refer to Truth Table I for more details.
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