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P4C174-15CM

Description
HIGH SPEED 8K x 8 CACHE TAG STATIC RAM
Categorystorage    storage   
File Size279KB,12 Pages
ManufacturerPyramid Semiconductor Corporation
Websitehttp://www.pyramidsemiconductor.com/
Download Datasheet Parametric View All

P4C174-15CM Overview

HIGH SPEED 8K x 8 CACHE TAG STATIC RAM

P4C174-15CM Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerPyramid Semiconductor Corporation
Parts packaging codeDIP
package instruction0.300 INCH, SIDE BRAZED, CERAMIC, DIP-28
Contacts28
Reach Compliance Codecompli
ECCN code3A001.A.2.C
Maximum access time15 ns
JESD-30 codeR-CDIP-T28
JESD-609 codee0
memory density65536 bi
Memory IC TypeCACHE TAG SRAM
memory width8
Number of functions1
Number of terminals28
word count8192 words
character code8000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize8KX8
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum seat height5.715 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTIN LEAD
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width7.62 mm
P4C174
HIGH SPEED 8K x 8
CACHE TAG STATIC RAM
FEATURES
High Speed Address-To-Match - 8 ns Maximum
Access Time
High-Speed Read-Access Time
– 8/10/12/15/20/25 ns (Commercial)
– 15/20/25 ns (Military)
Open Drain MATCH Output
Reset Function
8-Bit Tag Comparison Logic
Automatic Powerdown During Long Cycles
Data Retention at 2V for Battery Backup
Operation
Advanced CMOS Technology
Low Power Operation
Package Styles Available
— 28 Pin 300 mil DIP
— 28 Pin 300 mil Plastic SOJ
Single Power Supply
— 5V±10%
DESCRIPTION
The P4C174 is a 65,536 bit high speed cache tag static
RAM organized as 8K x 8. The CMOS memory has equal
access and cycle times. Inputs are fully TTL-compatible.
The cache tag RAMs operate from a single 5V±10%
power supply. An 8-bit data comparator with a MATCH
output is included for use as an address tag comparator
in high speed cache applications. The reset function
provides the capability to reset all memory locations to a
LOW level.
The MATCH output of the P4C174 reflects the compari-
son result between the 8-bit data on the I/O pins and
the addressed memory location. 8K Cache lines can be
mapped into 1M-Byte address spaces by comparing 20
address bits organized as 13-line address bits and 7-
page address bits.
Low power operation of the P4C174 is enhanced by
automatic powerdown when the memory is deselected or
during long cycle times. Also, data retention is main-
tained down to V
CC
= 2.0. Typical battery backup appli-
cations consume only 30
µ
W at V
CC
=
3.0V.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
DIP (C5, P5), SOJ (J5)
Document #
SRAM118
REV C
1
Revised August 2006
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