P4C174-12CMB datasheet, PDF - EEWORLD Datasheet

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P4C174-12CMB: DescriptionHIGH SPEED 8K x 8 CACHE TAG STATIC RAM; File Size279KB，12 Pages; ManufacturerPyramid Semiconductor Corporation; Websitehttp://www.pyramidsemiconductor.com/

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P4C174-12CMB Overview

HIGH SPEED 8K x 8 CACHE TAG STATIC RAM

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P4C174

HIGH SPEED 8K x 8

CACHE TAG STATIC RAM

FEATURES

High Speed Address-To-Match - 8 ns Maximum

Access Time

High-Speed Read-Access Time

– 8/10/12/15/20/25 ns (Commercial)

– 15/20/25 ns (Military)

Open Drain MATCH Output

Reset Function

8-Bit Tag Comparison Logic

Automatic Powerdown During Long Cycles

Data Retention at 2V for Battery Backup

Operation

Advanced CMOS Technology

Low Power Operation

Package Styles Available

— 28 Pin 300 mil DIP

— 28 Pin 300 mil Plastic SOJ

Single Power Supply

— 5V±10%

DESCRIPTION

The P4C174 is a 65,536 bit high speed cache tag static

RAM organized as 8K x 8. The CMOS memory has equal

access and cycle times. Inputs are fully TTL-compatible.

The cache tag RAMs operate from a single 5V±10%

power supply. An 8-bit data comparator with a MATCH

output is included for use as an address tag comparator

in high speed cache applications. The reset function

provides the capability to reset all memory locations to a

LOW level.

The MATCH output of the P4C174 reflects the compari-

son result between the 8-bit data on the I/O pins and

the addressed memory location. 8K Cache lines can be

mapped into 1M-Byte address spaces by comparing 20

address bits organized as 13-line address bits and 7-

page address bits.

Low power operation of the P4C174 is enhanced by

automatic powerdown when the memory is deselected or

during long cycle times. Also, data retention is main-

tained down to V

= 2.0. Typical battery backup appli-

cations consume only 30

W at V

3.0V.

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATION

DIP (C5, P5), SOJ (J5)

Document #

SRAM118

REV C

Revised August 2006

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