P4C169-55JC datasheet, PDF - EEWORLD Datasheet

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P4C169-55JC: DescriptionULTRA HIGH SPEED 4K x 4 STATIC CMOS RAMS; File Size235KB，15 Pages; ManufacturerPyramid Semiconductor Corporation; Websitehttp://www.pyramidsemiconductor.com/

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P4C169-55JC Overview

ULTRA HIGH SPEED 4K x 4 STATIC CMOS RAMS

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P4C168, P4C169, P4C170

ULTRA HIGH SPEED 4K x 4

STATIC CMOS RAMS

FEATURES

Full CMOS, 6T Cell

High Speed (Equal Access and Cycle Times)

– 12/15/20/25/35ns (Commercial)

– 20/25/35/45/55/70ns (P4C168 Military)

Low Power Operation (Commercial)

– 715 mW Active

– 193 mW Standby (TTL Input) P4C168

– 83 mW Standby (CMOS Input) P4C168

Single 5V±10% Power Supply

Fully TTL Compatible, Common I/O Ports

Three Options

– P4C168 Low Power Standby Mode

– P4C169 Fast Chip Select Control

– P4C170 Fast Chip Select, Output Enable

Controls

Standard Pinout (JEDEC Approved)

– P4C168: 20-pin DIP, SOJ, LCC, SOIC,

CERPACK, and Flat Pack

– P4C169: 20-pin DIP and SOIC

– P4C170: 22-pin DIP

DESCRIPTION

The P4C168, P4C169 and P4C170 are a family of

16,384-bit ultra high-speed static RAMs organized as 4K

x 4. All three devices have common input/output ports.The

P4C168 enters the standby mode when the chip enable

(CE) control goes HIGH; with CMOS input levels, power

consumption is only 83mW in this mode. Both the P4C169

and the P4C170 offer a fast chip select access time that

is only 67% of the address access time. In addition, the

P4C170 includes an output enable (OE) control to elimi-

nate data bus contention. The RAMs operate from a

single 5V ± 10% tolerance power supply.

Access times as fast as 12 nanoseconds are available,

permitting greatly enhanced system operating speeds.

CMOS is used to reduce power consumption to a low 715

mW active, 193 mW standby.

The P4C168 and P4C169 are available in 20-pin (P4C170

in 22-pin) 300 mil DIP packages providing excellent

board level densities. The P4C168 is also available in 20-

pin 300 mil SOIC, SOJ, CERPACK, and Flat Pack

packages.

The P4C169 is also available in a 20-pin 300 mil SOIC

package.

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATIONS

P4C168

P4C169

DIP (P2, C6, D2)

DIP (P2)

SOIC (S2)

SOJ (J2)

CERPACK (F2)

SOLDER SEAL FLAT PACK (FS-2)

P4C170

DIP (P3)

Document #

SRAM107

REV A

Revised October 2005

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