P4C165
ULTRA HIGH SPEED 8K x 8
RESETTABLE STATIC CMOS RAM
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 15/20/25 ns (Commercial)
– 20/25/35 (Industrial)
Low Power Operation
Chip Clear Function
Output Enable and Dual Chip Enable Control
Functions
Single 5V±10% Power Supply
Common Data I/O
Fully TTL Compatible Inputs and Outputs
Standard Pinout (JEDEC Approved)
– 28-Pin Plastic DIP (300 mil)
DESCRIPTION
The P4C165 is a 65,536-bit ultra high-speed static RAM
organized as 8K x 8. The RAM features a reset control to
enable clearing all words to zero within two cycle times.
The CMOS memory requires no clocks or refreshing and
has equal access and cycle times. Inputs are fully TTL-
compatible. The RAM operates from a single 5V±10%
tolerance power supply.
Access times as fast as 15 nanoseconds are available,
permitting greatly enhanced system operating speeds.
In full standby mode with CMOS inputs, power consump-
tion is only 5.5 mW for the P4C165.
The P4C165 is available in a 28-pin 300 mil DIP.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
1519B
DIP (P5)
Document #
SRAM117
Rev OR
1
Revised October 2005
P4C165
MAXIMUM RATINGS
(1)
Symbol
V
CC
Parameter
Power Supply Pin with
Respect to GND
Terminal Voltage with
Respect to GND
(up to 7.0V)
Operating Temperature
Value
–0.5 to +7
–0.5 to
V
CC
+0.5
–55 to +125
Unit
V
Symbol
T
BIAS
T
STG
P
T
I
OUT
Parameter
Temperature Under
Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
–55 to +125
–65 to +150
1.0
50
Unit
°C
°C
W
mA
V
TERM
T
A
V
°C
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade(2)
Commercial
Industrial
Ambient
Temperature
0°C to +70°C
–40°C to +85°C
GND
0V
0V
V
CC
5.0V ± 10%
5.0V ± 10%
CAPACITANCES
(4)
V
CC
= 5.0V, T
A
= 25°C, f = 1.0MHz
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions Typ. Unit
V
IN
= 0V
V
OUT
= 0V
5
7
pF
pF
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage
(2)
Symbol
V
IH
V
IL
V
HC
V
LC
V
CD
V
OL
V
OH
I
LI
I
LO
I
SB
Parameter
Input High Voltage
Input Low Voltage
CMOS Input High Voltage
CMOS Input Low Voltage
Input Clamp Diode Voltage
Output Low Voltage
(TTL Load)
Output High Voltage
(TTL Load)
Input Leakage Current
Output Leakage Current
Standby Power Supply Current
(TTL Input Levels)
Standby Power Supply Current
(CMOS Input Levels)
V
CC
= Min., I
IN
= –18 mA
I
OL
= +8 mA, V
CC
= Min.
I
OH
= –4 mA, V
CC
= Min.
V
CC
= Max.
V
IN
= GND to V
CC
V
CC
= Max.,
CE
= V
IH
,
V
OUT
= GND to V
CC
CE
≥
V
IH
or
CE
2
≤V
IL
, V
CC
= Max
f = Max., Outputs Open
CE
≥
V
HC
or
CE
2
≤V
LC
, V
CC
= Max
f = 0, Outputs Open
V
IN
≤
V
LC
or V
IN
≥
V
HC
Ind./Com’l.
Ind./Com’l.
–5
___
+5
30
µA
mA
Ind./Com’l.
–5
+5
µA
2.4
Test Conditions
P4C165
Min
Max
2.2
–0.5
(3)
–0.5
(3)
V
CC
+0.5
0.8
0.2
–1.2
0.4
Unit
V
V
V
V
V
V
V
V
CC
–0.2 V
CC
+0.5
I
SB1
Ind./Com’l.
___
15
mA
n/a = Not Applicable
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
Document #
SRAM117
Rev OR
2
Page 2 of 9
P4C165
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol
I
CC
Parameter
Dynamic Operating Current*
Temperature Range
Commercial
Industrial
–15
160
N/A
–20
155
160
–25
150
155
–35
N/A
150
Unit
mA
mA
*V
CC
= 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V.
CE
1
= V
IL
, CE
2
= V
IH
,
OE
= V
IH
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Sym.
t
RC
t
AA
t
AC
t
OH
t
LZ
t
HZ
t
OE
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Hold from Address Change
Chip Enable to Output in Low Z
Chip Disable to Output in High Z
Output Enable Low to Data Valid
-15
15
15
15
3
2
8
9
2
9
0
15
0
2
3
2
-20
20
20
20
3
2
8
10
2
9
0
20
-25
25
25
25
3
2
10
13
2
12
0
20
-35
35
35
35
Min Max Min Max Min Max Min Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
18
15
t
OLZ
Output Enable Low to Low Z
t
OHZ
Output Enable High to High Z
t
PU
t
PD
Chip Enable to Power Up Time
Chip Disable to Power Down Time
20
ns
Document #
SRAM117
Rev OR
3
Page 3 of 9
P4C165
READ CYCLE NO. 1 (OE CONTROLLED)
(5)
OE
READ CYCLE NO. 2 (ADDRESS CONTROLLED)
(5,6)
READ CYCLE NO. 3 (CE
1
, CE
2
CONTROLLED)
(5,7,10)
CE
Notes:
5.
WE
is HIGH for READ cycle.
6.
CE
1
is LOW, CE
2
is HIGH and
OE
is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with
CE
1
transition
LOW and CE
2
transition HIGH.
8. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
9. READ Cycle Time is measured from the last valid address to the first
transitioning address.
10. Transitions caused by a chip enable control have similar delays
irrespective of whether
CE
1
or CE
2
causes them.
Document #
SRAM117
Rev OR
4
Page 4 of 9
P4C165
AC CHARACTERISTICS—WRITE CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Sym.
t
WC
t
CW
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
OW
Parameter
Write Cycle Time
Chip Enable Time to End of Write
Address Valid to End of Write
Address Set-up Time
Write Pulse Width
Address Hold Time
Data Valid to End of Write
Date Hold Time
Write Enable to Output in High Z
Output Active from End of Write
-15
15
12
12
0
12
0
9
0
7
3
3
-20
20
15
15
0
15
0
11
0
8
3
-25
25
18
18
0
18
0
13
0
10
3
-35
35
25
25
0
20
0
15
0
14
Min Max Min Max Min Max Min Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WRITE CYCLE NO. 1 (WE CONTROLLED)
(11)
WE
Notes:
11.
CE
1
and
WE
must be LOW, and CE
2
HIGH for WRITE cycle.
12.
OE
is LOW for this WRITE cycle to show t
WZ
and t
OW
.
13. If
CE
1
goes HIGH, or CE
2
goes LOW, simultaneously with
WE
HIGH,
the output remains in a high impedance state.
14. Write Cycle Time is measured from the last valid address to the first
transitioning address.
Document #
SRAM117
Rev OR
5
Page 5 of 9
京公网安备 11010802033920号
EEWORLD
