ABRIDGED DATA SHEET
19-4835; Rev 6; 8/09
DS34T101/DS34T102/DS34T104/DS34T108
Single/Dual/Quad/Octal TDM-over-Packet Chip
General Description
These IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC
compliant devices allow up to eight E1, T1 or serial
streams or one high-speed E3, T3, STS-1 or serial
stream to be transported transparently over IP, MPLS
or Ethernet networks. Jitter and wander of recovered
clocks conform to G.823/G.824, G.8261, and TDM
specifications. TDM data is transported in up to 64
individually configurable bundles. All standards-
based TDM-over-packet mapping methods are
supported except AAL2. Frame-based serial HDLC
data flows are also supported. With built-in full-
featured E1/T1 framers and LIUs. These ICs
encapsulate the TDM-over-packet solution from
analog E1/T1 signal to Ethernet MII while preserving
options to make use of TDM streams at key
intermediate points. The high level of integration
available with the DS34T10x devices minimizes cost,
board space, and time to market.
Features
Full-Featured IC Includes E1/T1 LIUs and
Framers, TDMoP Engine, and 10/100 MAC
Transport of E1, T1, E3, T3 or STS-1 TDM or
CBR Serial Signals Over Packet Networks
Full Support for These Mapping Methods:
SAToP, CESoPSN, TDMoIP (AAL1), HDLC,
Unstructured, Structured, Structured with CAS
Adaptive Clock Recovery, Common Clock,
External Clock and Loopback Timing Modes
On-Chip TDM Clock Recovery Machines, One
Per Port, Independently Configurable
Clock Recovery Algorithm Handles Network
PDV, Packet Loss, Constant Delay Changes,
Frequency Changes and Other Impairments
64 Independent Bundles/Connections
Multiprotocol Encapsulation Supports IPv4,
IPv6, UDP, RTP, L2TPv3, MPLS, Metro Ethernet
VLAN Support According to 802.1p and 802.1Q
10/100 Ethernet MAC Supports MII/RMII/SSMII
Selectable 32-Bit, 16-Bit or SPI Processor Bus
Operates from Only Two Clock Signals, One for
Clock Recovery and One for Packet Processing
Glueless SDRAM Buffer Management
Low-Power 1.8V Core, 3.3V I/O
Applications
TDM Circuit Extension Over PSN
o
Leased-Line Services Over PSN
o
TDM Over GPON/EPON
o
TDM Over Cable
o
TDM Over Wireless
Cellular Backhaul Over PSN
Multiservice Over Unified PSN
HDLC-Based Traffic Transport Over PSN
See detailed feature list in Section
5.
Functional Diagram
CPU
Bus
Ordering Information
PART
DS34T101GN
DS34T101GN+
DS34T102GN
DS34T102GN+
DS34T104GN
DS34T104GN+
DS34T108GN
DS34T108GN+
PORTS TEMP RANGE
1
1
2
2
4
4
8
8
-40C to +85C
-40C to +85C
-40C to +85C
-40C to +85C
-40C to +85C
-40C to +85C
-40C to +85C
-40C to +85C
PIN-PACKAGE
484 TEBGA
484 TEBGA
484 TEBGA
484 TEBGA
484 TEBGA
484 TEBGA
484 HSBGA
484 HSBGA
DS34T108
Octal
E1/T1/J1
Transceiver
Framers
Circuit
Emulation
Engine
10/100
Ethernet
MAC
xMII
E1/T1
Interfaces
BERT
& CAS
LIUs
Buffer
Manager
Clock
Adapters
TDM
Access
SDRAM
Interface
Clock Inputs
+Denotes
a lead(Pb)-free/RoHS-compliant package (explanation).
________________________________________________________
Maxim Integrated Products
1
Some revisions of this device may incorporate deviations from published specifications known as errata.
Multiple revisions of any device may be simultaneously available through various sales channels. For
information about device errata, go to:
www.maxim-ic.com/errata.
For pricing, delivery, and ordering
information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
ABRIDGED DATA SHEET
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
1 Applicable Standards
Table 1-1. Applicable Standards
SPECIFICATION
ANSI
T1.102
T1.107
T1.231.02
T1.403
AT&T
TR54016
TR62411
ETSI
ETS 300 011
ETS 300 166
ETS 300 233
IEEE
IEEE 802.3
IEEE 1149.1
IETF
RFC 4553
RFC 4618
RFC 5086
RFC 5087
ITU-T
G.703
G.704
G.706
G.732
G.736
G.775
G.823
G.824
G.8261/Y.1361
I.363.1
I.363.2
I.366.2
I.431
I.432
O.151
Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and
Physical Layer Specifications
(2005)
Standard Test Access Port and Boundary-Scan Architecture,
1990
Structure-Agnostic Time Division Multiplexing (TDM) over Packet (SAToP)
(06/2006)
Encapsulation Methods for Transport of PPP/High-Level Data Link Control (HDLC) over
MPLS Networks
(09/2006)
Structure-Aware Time Division Multiplexed (TDM) Circuit Emulation Service over Packet
Switched Network (CESoPSN)
(12/2007)
Time Division Multiplexing over IP (TDMoIP)
(12/2007)
Physical/Electrical Characteristics of Hierarchical Digital Interfaces
(11/2001)
Synchronous Frame Structures Used at 1544, 6312, 2048, 8448 and 44736 kbit/s
Hierarchical Levels
(10/1998)
Frame Alignment and Cyclic Redundancy Check (CRC) Procedures Relating to Basic Frame
Structures Defined in Recommendation G.704
(1991)
Characteristics of primary PCM Multiplex Equipment Operating at 2048Kbit/s
(11/1988)
Characteristics of Synchronous Digital Multiplex Equipment Operating at 2048Kbit/s
(03/1993)
Loss of Signal (LOS) and Alarm Indication Signal (AIS) and Remote Defect Indication (RD)
Defect Detection and Clearance Criteria for PDH Signals
(10/1998)
The Control of Jitter and Wander within Digital Networks which are Based on the 2048kbps
Hierarchy
(03/2000)
The Control of Jitter and Wander within Digital Networks which are Based on the 1544kbps
Hierarchy
(03/2000)
Timing and Synchronization Aspects in Packet Networks
(05/2006)
B-ISDN ATM Adaptation Layer Specification: Type 1 AAL
(08/1996)
B-ISDN ATM Adaptation Layer Specification: Type 2 AAL
(11/2000)
AAL Type 2 Service Specific Convergence Sublayer for Narrow-Band Services
(11/2000)
Primary rate user-network interface - Layer 1 specification
(03/1993)
B-ISDN User-Network Interface – Physical Layer Specification (03/1993)
Error Performance Measuring Equipment Operating at the Primary Rate and Above
(1992)
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SPECIFICATION TITLE
Digital Hierarchy—Electrical Interfaces,
1993
Digital Hierarchy—Formats Specification,
1995
Digital Hierarchy—Layer 1 In-Service Digital Transmission Performance Monitoring,
2003
Network and Customer Installation Interfaces—DS1 Electrical Interface,
1999
Requirements for Interfacing Digital Terminal Equipment to Services Employing the Extended
Superframe Format
(9/1989)
ACCUNET® T1.5 Service Description and Interface Specification
(12/1990)
Integrated Services Digital Network (ISDN); Primary rate User Network Interface (UNI); Part
1: Layer 1 Specification
V1.2.2 (2000-05)
Transmission and Multiplexing (TM); Physical and Electrical Characteristics of Hierarchical
Digital Interfaces for Equipment Using the 2 048 kbit/s - Based Plesiochronous or
Synchronous Digital Hierarchies
V1.2.1 (2001-09)
Integrated Services Digital Network (ISDN);Access Digital Section for ISDN Primary Rate,
ed.1
(1994-05)
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____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
SPECIFICATION
O.161
Y.1413
Y.1414
Y.1452
Y.1453
MEF
MEF 8
MFA
MFA 4.0
MFA 5.0.0
MFA 8.0.0
SPECIFICATION TITLE
In-Service Code Violation Monitors for Digital Systems
(1993)
TDM-MPLS Network Interworking – User Plane Interworking
(03/2004)
Voice Services–MPLS Network Interworking
(07/2004)
Voice Trunking over IP Networks
(03/2006)
TDM-IP Interworking – User Plane Networking
(03/2006)
Implementation Agreement for the Emulation of PDH Circuits over Metro Ethernet Networks
(10/2004)
TDM Transport over MPLS Using AAL1
(06/2003)
I.366.2 Voice Trunking Format over MPLS Implementation Agreement (08/2003)
Emulation of TDM Circuits over MPLS Using Raw Encapsulation – Implementation
Agreement
(11/2004)
2 Detailed Description
The DS34T108 is an 8-port device integrating a sophisticated multiport TDM-over-Packet (TDMoP) core and eight
full-featured, independent, software-configurable E1/T1 transceivers. The DS34T104, DS34T102 and DS34T101
have the same functionality as the DS34T108, except they have only 4, 2 or 1 ports and transceivers, respectively.
Each E1/T1 transceiver is composed of a line interface unit (LIU), a framer, an elastic store, an HDLC controller
and a bit error rate tester (BERT) block. These transceivers connect seamlessly to the TDMoP block to form a
complete solution for mapping and demapping E1/T1 to and from IP, MPLS or Ethernet networks. A MAC built into
the TDMoP block supports connectivity to a single 10/100 Mbps PHY over an MII, RMII or SSMII interface. The
DS34T10x devices are controlled through a 16 or 32-bit parallel bus interface or a high-speed SPI serial interface.
TDM-over-Packet Core
The TDM-over-Packet (TDMoP) core is the enabling block for circuit emulation and other network applications. It
performs transparent transport of legacy TDM traffic over Packet Switched-Networks (PSN). The TDMoP core
implements payload mapping methods such as AAL1 for circuit emulation, HDLC method, structure-agnostic
SAToP method, and the structure-aware CESoPSN method.
The AAL1 payload-type machine maps and demaps E1, T1, E3, T3, STS-1 and other serial data flows into and out
of IP, MPLS or Ethernet packets, according to the methods described in ITU-T Y.1413, Y.1453, MEF 8, MFA 4.1
and IETF RFC 5087 (TDMoIP). It supports E1/T1 structured mode with or without CAS, using a timeslot size of 8
bits, or unstructured mode (carrying serial interfaces, unframed E1/T1 or E3/T3/STS-1 traffic).
The HDLC payload-type machine maps and demaps HDLC dataflows into and out of IP/MPLS packets according
to IETF RFC 4618 (excluding clause 5.3 – PPP) and IETF RFC 5087 (TDMoIP). It supports 2-, 7- and 8-bit timeslot
resolution (i.e. 16, 56, and 64 kbps respectively), as well as N × 64 kbps bundles (n=1 to 32). Supported
applications of this machine include trunking of HDLC-based traffic (such as Frame Relay) implementing Dynamic
Bandwidth Allocation over IP/MPLS networks and HDLC-based signaling interpretation (such as ISDN D-channel
signaling termination – BRI or PRI, V5.1/2, or GR-303).
The SAToP payload-type machine maps and demaps unframed E1, T1, E3 or T3 data flows into and out of IP,
MPLS or Ethernet packets according to ITU-T Y.1413, Y.1453, MEF 8, MFA 8.0.0 and IETF RFC 4553. It supports
E1/T1/E3/T3 with no regard for the TDM structure. If TDM structure exists it is ignored, allowing this to be the
simplest mapping/demapping method. The size of the payload is programmable for different services. This
emulation suits applications where the provider edges have no need to interpret TDM data or to participate in the
TDM signaling. The PSN network must have almost no packet loss and very low packet delay variation (PDV) for
this method.
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The CESoPSN payload-type machine maps and demaps structured E1, T1, E3 or T3 data flows into and out of IP,
MPLS or Ethernet packets with static assignment of timeslots inside a bundle according to ITU-T Y.1413, Y.1453,
MEF 8, MFA 8.0.0 and the IETF RFC 5086 (CESoPSN). It supports E1/T1/E3/T3 while taking into account the
TDM structure. The level of structure must be chosen for proper payload conversion such as the framing type (i.e.
frame or multiframe). This method is less sensitive to PSN impairments but lost packets could still cause service
interruption.
E1/T1 Transceivers
The LIU in each transceiver is composed of a transmitter, a receiver and a jitter attenuator. Internal software
configurable impedance matching is provided for both transmit and receive paths, reducing external component
count. The transmit interface is responsible for generating the necessary waveshapes for driving the E1/T1 twisted
pair or coax cable and providing the correct source impedance depending on the type of cable used. T1 waveform
generation includes DSX–1 line build-outs as well as CSU line build-outs of 0dB, -7.5dB, -15dB, and -22.5dB. E1
waveform generation includes G.703 waveshapes for both 75 coax and 120 twisted cables. The receive
interface provides the correct line termination and recovers clock and data from the incoming line. The receive
sensitivity adjusts automatically to the incoming signal level and can be programmed for 0dB to -43dB or 0dB to
-12dB for E1 applications and 0dB to -15dB or 0dB to -36dB for T1 applications. The jitter attenuator removes
phase jitter from the transmitted or received signal. The crystal-less jitter attenuator can be placed in either the
transmit or receive path and requires only a T1- or E1-rate reference clock, which is typically synthesized by the
CLAD1 block from a common reference frequency of 10MHz, 19.44MHz, 38.88MHz or 77.76MHz.
In the framer block, the transmit formatter takes data from the TDMoP core, inserts the appropriate framing
patterns and alarm information, calculates and inserts CRC codes, and provides the HDB3 or B8ZS encoding (zero
code suppression) and AMI line coding. The receive framer decodes AMI, HDB3 and B8ZS line coding, finds frame
and multiframe alignment in the incoming data stream, reports alarm information, counts framing/coding/CRC
errors, and provides clock, data, and frame-sync signals to the TDMoP core.
Both transmit and receive paths have built-in HDLC controller and BERT blocks. The HDLC blocks can be
assigned to any timeslot, a portion of a timeslot or to the FDL (T1) or Sa bits (E1). Each controller has 64-byte
FIFOs, reducing the amount of processor overhead required to manage the flow of data. The BERT blocks can
generate and synchronize with pseudo-random and repetitive patterns, insert errors (singly or at a constant error
rate) and detect and count errors to calculate bit error rates.
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3 Application Examples
In
Figure 3-1,
a DS34T10x device is used in each TDMoP gateway to map TDM services into a packet-switched
metropolitan network. TDMoP data is carried over various media: fiber, wireless, G/EPON, coax, etc.
Figure 3-1. TDMoP in a Metropolitan Packet Switched Network
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