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P4C164-35JCLF

Description
ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAMS
Categorystorage    storage   
File Size184KB,16 Pages
ManufacturerPyramid Semiconductor Corporation
Websitehttp://www.pyramidsemiconductor.com/
Environmental Compliance
Download Datasheet Parametric View All

P4C164-35JCLF Overview

ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAMS

P4C164-35JCLF Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerPyramid Semiconductor Corporation
Parts packaging codeSOJ
package instructionSOJ, SOJ28,.34
Contacts28
Reach Compliance Codecompliant
ECCN codeEAR99
Maximum access time35 ns
I/O typeCOMMON
JESD-30 codeR-PDSO-J28
JESD-609 codee3
length18.161 mm
memory density65536 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals28
word count8192 words
character code8000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize8KX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeSOJ
Encapsulate equivalent codeSOJ28,.34
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Certification statusNot Qualified
Maximum seat height3.7592 mm
Maximum standby current0.015 A
Minimum standby current4.5 V
Maximum slew rate0.145 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMATTE TIN
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width7.5184 mm
Base Number Matches1
P4C164
ULTRA HIGH SPEED 8K x 8
STATIC CMOS RAMS
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 8/10/12/15/20/25/35/70/100 ns (Commercial)
– 10/12/15/20/25/35/70/100 ns(Industrial)
– 12/15/20/25/35/45/70/100 ns (Military)
Low Power Operation
Output Enable and Dual Chip Enable Control
Functions
Single 5V±10% Power Supply
Data Retention with 2.0V Supply, 10 µA Typical
Current (P4C164L Military)
Common Data I/O
Fully TTL Compatible Inputs and Outputs
Standard Pinout (JEDEC Approved)
– 28-Pin 300 mil Plastic DIP, SOJ
– 28-Pin 600 mil Plastic DIP (70 & 100ns)
– 28-Pin 300 mil SOP (70 & 100ns)
– 28-Pin 300 mil Ceramic DIP
– 28-Pin 600 mil Ceramic DIP
– 28-Pin 350 x 550 mil LCC
– 32-Pin 450 x 550 mil LCC
– 28-Pin CERPACK
DESCRIPTION
The P4C164 is a 65,536-bit ultra high-speed static RAM
organized as 8K x 8. The CMOS memory requires no
clocks or refreshing and has equal access and cycle
times. Inputs are fully TTL-compatible. The RAM operates
from a single 5V±10% tolerance power supply. With
battery backup, data integrity is maintained with supply
voltages down to 2.0V. Current drain is typically 10 µA
from a 2.0V supply.
Access times as fast as 8 nanoseconds are available,
permitting greatly enhanced system operating speeds.
The P4C164 is available in 28-pin 300 mil DIP and SOJ, 28-
pin 600 mil plastic and ceramic DIP, 28-pin 350 x 550 mil
LCC, 32-pin 450 x 550 mil LCC, and 28-pin CERPACK.
The 70ns and 100ns P4C164s are available in the 600 mil
plastic DIP.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
DIP (P5, P6, C5, C5-1, D5-1, D5-2),
SOJ (J5), CERPACK (F4), SOP(S6)
SEE PAGE 7 FOR LCC PIN CONFIGURATIONS
1519B
Document #
SRAM115
REV F
Revised June 2007
1
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