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P4C150-35CMB

Description
ULTRA HIGH SPEED 1K X 4 RESETTABLE STATIC CMOS RAM
Categorystorage    storage   
File Size214KB,11 Pages
ManufacturerPyramid Semiconductor Corporation
Websitehttp://www.pyramidsemiconductor.com/
Download Datasheet Parametric View All

P4C150-35CMB Overview

ULTRA HIGH SPEED 1K X 4 RESETTABLE STATIC CMOS RAM

P4C150-35CMB Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerPyramid Semiconductor Corporation
Parts packaging codeDIP
package instructionDIP,
Contacts24
Reach Compliance Codecompliant
ECCN code3A001.A.2.C
Maximum access time35 ns
JESD-30 codeR-CDIP-T24
JESD-609 codee0
memory density4096 bit
Memory IC TypeCACHE SRAM
memory width4
Number of functions1
Number of terminals24
word count1024 words
character code1000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize1KX4
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Filter levelMIL-STD-883 Class B
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTIN LEAD
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width7.62 mm
P4C150
ULTRA HIGH SPEED 1K X 4
RESETTABLE STATIC CMOS RAM
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25 ns (Commercial)
– 15/20/25/35 ns (Military)
Chip Clear Function
Low Power Operation
Single 5V ± 10% Power Supply
Separate Input and Output Ports
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Standard Pinout (JEDEC Approved)
– 24-Pin 300 mil DIP
– 24-Pin 300 mil SOIC
– 28-Pin LCC (350 x 550 mils)
– 24-Pin CERPACK
DESCRIPTION
The P4C150 is a 4,096-bit ultra high-speed static RAM
organized as 1K x 4 for high speed cache applications.
The RAM features a reset control to enable clearing all
words to zero within two cycle times. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs and outputs are fully TTL-
compatible. The RAM operates from a single 5V ± 10%
tolerance power supply.
Access times as fast as 10 nanoseconds are available
permitting greatly enhanced system operating speeds.
Time required to reset is only 20 ns for the 10 ns SRAM.
CMOS is used to reduce power consumption to a low
level.
The P4C150 is available in 24-pin 300 mil DIP and SOIC
packages providing excellent board level densities.
The device is also available in a 28-pin LCC package as
well as a 24-pin FLATPACK for military applications.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
DIP (P4, C4, D4), SOIC (S4)
CERPACK (F3) SIMILAR
LCC (L5)
Document #
SRAM105
REV A
1
Revised October 2005
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