P4C148, P4C149
ULTRA HIGH SPEED 1K x 4
STATIC CMOS RAMS
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25/35/45/55 ns (Commercial)
– 15/20/25/35/45/55 ns (P4C148 Military)
Low Power Operation
Single 5V ± 10% Power Supply
Two Options
– P4C148 Low Power Standby Mode
– P4C149 Fast Chip Select Control
Common Input/Output Ports
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Standard Pinout (JEDEC Approved)
– 18 Pin 300 mil DIP
– 18 Pin LCC (295 x 335 mil) [P4C148 only]
– 18 Pin LCC (290 x 430 mil)
DESCRIPTION
The P4C148 and P4C149 are 4,096-bit ultra high-speed
static RAMs organized as 1K x 4. Both devices have
common input/output ports. The P4C148 enters the
standby mode when the chip enable (CE) goes HIGH;
with CMOS input levels, power consumption is extremely
low in this mode. The P4C149 features a fast chip select
capability using
CS.
The CMOS memories require no
clocks or refreshing, and have equal access and cycle
times. Inputs are fully TTL-compatible. The RAMs
operate from a single 5V
±
10% tolerance power supply.
Access times as fast as 10 nanoseconds are available,
permitting greatly enhanced system operating speeds.
CMOS is used to reduce power consumption when
active; for the P4C148, consumption is further reduced in
the standby mode.
The P4C148 and P4C149 are available in 18-pin 300 mil
DIP packages, as well as 2 different LCC packages,
providing excellent board level densities.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
P4C148 DIP (C9, D1, P1)
P4C149 DIP (P1)
P4C148 LCC (L7, L7-1)
P4C149 LCC (L7)
Document #
SRAM104
REV B
1
Revised April 2007
P4C148/P4C149
MAXIMUM RATINGS
(1)
Symbol
V
CC
Parameter
Power Supply Pin with
Respect to GND
Terminal Voltage with
Respect to GND
(up to 7.0V)
Operating Temperature
Value
– 0.5 to +7
– 0.5 to
V
CC
+0.5
– 55 to +125
Unit
V
Symbol
T
BIAS
T
STG
P
T
I
OUT
Parameter
Temperature Under
Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
– 55 to +125
– 65 to +150
1.0
50
Unit
°C
°C
W
mA
V
TERM
T
A
V
°C
RECOMMENDED OPERATING
CONDITIONS
Grade
(2)
Commercial
Military
Ambient Temp
0°C to 70°C
-55°C to +125°C
Gnd
0V
0V
V
CC
5.0V
± 10%
5.0V
± 10%
CAPACITANCES
(4)
(V
CC
= 5.0V, T
A
= 25°C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Conditions Typ. Unit
V
IN
= 0V
5
7
pF
pF
Output Capacitance V
OUT
= 0V
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage (2)
Sym.
V
OH
V
OL
V
IH
V
IL
I
LI
I
LO
I
SB
I
SB1
Parameter
Output High Voltage
(TTL Load)
Output Low Voltage
(TTL Load)
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage Current
V
CC
= Max., V
IN
= GND to V
CC
V
CC
= Max.,
CE, CS
= V
IH
,
V
OUT
= GND to V
CC
Mil.
Comm’l
Mil.
Comm’l
Mil.
Comm’l
Mil.
Comm’l
Test Conditions
I
OH
= –4 mA, V
CC
= Min.
I
OL
= +8 mA, V
CC
= Min
2.2
–0.5
(3)
–10
–5
–10
–5
P4C148
Min.
2.4
0.4
V
CC
+0.5
0.8
+10
+5
+10
+5
30
23
15
10
2.2
–0.5
(3)
–10
–5
–10
–5
Max.
P4C149
Min.
2.4
0.4
V
CC
+0.5
0.8
+10
+5
+10
+5
N/A
N/A
N/A
N/A
Max.
Unit
V
V
V
V
µA
µA
mA
mA
Standby Power Supply
CE
≥
V
IH
, V
CC
= Max.,
Current (TTL Input Levels) f=Max., Outputs Open
Standby Power Supply
Current
(CMOS Input Levels)
CE
≥
V
HC
, V
CC
= Max., f= 0,
Outputs Open
V
IN
≤
0.2V or V
IN
≥
V
CC
–0.2V
N/A = Not Applicable
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol Parameter
I
CC
Dynamic Operating Current
Temperature Range
Commercial
Military
-10 -12 -15 -20 -25 -35 -45 -55 Unit
130 130 120 115 100 100 95
95
mA
N/A N/A 145 135 125 120 115 115 mA
Document #
SRAM104
REV B
Page 2 of 10
P4C148/P4C149
AC CHARACTERISTICS—READ CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Sym
t
RC
t
AA
t
AC
t
AC
t
OH
t
LZ
t
HZ
t
RCS
t
RCH
t
PU
t
PD
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time (P4C148)
Chip Enable Access Time (P4C149)
Output Hold from Address Change
Chip Enable to Output in Low Z (P4C149)
Chip Disable to Output in High Z (P4C149)
Read Command Setup Time
Read Command Hold Time
Chip Enable to Power Up Time (P4C148)
Chip Disable to Power Down Time (P4C148)
0
0
0
10
3
2
4
0
0
0
12
-10
-12
-15
-20
-25
-35
-45
-55
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
10
12
15
20
25
35
45
55
10
10
8
3
2
5
0
0
0
15
12
12
10
3
2
6
0
0
0
20
15
15
12
3
2
8
0
0
0
25
20
20
14
3
2
10
0
0
0
35
25
25
15
3
2
14
0
0
0
45
35
35
20
3
2
18
0
0
0
55
45
45
20
3
2
20
55
55
25
TIMING WAVEFORM OF READ CYCLE
TIMING WAVEFORM OF READ CYCLE NO. 2
(6)
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to MAXIMUM rating condi-
tions for extended periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet
per minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
5.
CE
is LOW and
WE
is HIGH for READ cycle.
6.
WE
is HIGH, and address must be valid prior to or coincident with
CE
transition LOW.
7. Transition is measured ±200mV from steady state voltage prior to
change with specified loading in Figure 1. This parameter is
sampled and not 100% tested.
8. Read Cycle Time is measured from the last valid address to the first
transitioning address.
Document #
SRAM104
REV B
Page 3 of 10
P4C148/P4C149
AC CHARACTERISTICS—WRITE CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Sym
Parameter
t
WC
Write Cycle Time
t
CW
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
OW
Chip Enable Time to End of Write
Address Valid to End of Write
Address Set-up Time
Write Pulse Width
Address Hold Time from End of Write
Data Valid to End of Write
Data Hold Time
Write Enable to Output in High Z
Output Active from End of Write
0
-10
-12
-15
-20
-25
-35
-45
-55
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
10
12
15
20
25
35
45
55
8
8
0
8
0
5
0
5
0
10
10
0
10
0
6
0
6
0
12
12
0
12
0
7
0
7
0
16
16
0
16
0
9
0
7
0
20
20
0
20
0
12
0
8
0
25
25
0
25
0
16
0
12
0
30
30
0
30
0
20
0
15
0
35
35
0
35
0
25
0
20
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)
(9)
WE
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE
CS
CONTROLLED)
(9)
CE/CS
CE
Notes:
9.
CE
and
WE
must be LOW for WRITE cycle.
10. If
CE
goes HIGH simultaneously with
WE
high, the output remains in a high impedance state.
11. Write Cycle Time is measured from the last valid address to the first transition address.
Document #
SRAM104
REV B
Page 4 of 10
P4C148/P4C149
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figures 1 and 2
TRUTH TABLE
Mode
Standby
Read
Write
CE
H
L
L
WE
X
H
L
Output
High Z
D
OUT
High Z
Power
Standby
Active
Active
Figure 1. Output Load
* including scope and test fixture.
Figure 2. Thevenin Equivalent
Note:
Due to the ultra-high speed of the P4C148/149, care must be taken
when testing this device; an inadequate setup can cause a normal
functioning part to be rejected as faulty. Long high-inductance leads that
cause supply bounce must be avoided by bringing the V
CC
and ground
planes directly up to the contactor fingers. A 0.01 µF high frequency
capacitor is also required between V
CC
and ground. To avoid signal
reflections, proper termination must be used; for example, a 50Ω test
environment should be terminated into a 50Ω load with 1.73V (Thevenin
Voltage) at the comparator input, and a 116Ω resistor must be used in
series with D
OUT
to match 166Ω (Thevenin Resistance).
Document #
SRAM104
REV B
Page 5 of 10
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