P4C1048L-70TC datasheet, PDF - EEWORLD Datasheet

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P4C1048L-70TC: DescriptionLOW POWER 512K x 8 CMOS STATIC RAM; Categorystorage storage; File Size157KB，12 Pages; ManufacturerPyramid Semiconductor Corporation; Websitehttp://www.pyramidsemiconductor.com/

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P4C1048L-70TC Overview

LOW POWER 512K x 8 CMOS STATIC RAM

P4C1048L-70TC Parametric

Parameter Name	Attribute value
Maker	Pyramid Semiconductor Corporation
Parts packaging code	TSOP2
package instruction	TSOP2,
Contacts	32
Reach Compliance Code	compli
ECCN code	3A991.B.2.A
Maximum access time	70 ns
JESD-30 code	R-PDSO-G32
JESD-609 code	e0
length	20.96 mm
memory density	4194304 bi
Memory IC Type	STANDARD SRAM
memory width	8
Number of functions	1
Number of terminals	32
word count	524288 words
character code	512000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512KX8
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum seat height	1.04 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
width	10.16 mm

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P4C1048L

LOW POWER 512K x 8

CMOS STATIC RAM

FEATURES

Current

— Operating: 35mA

— CMOS Standby: 100µA

Access Times

—45/55/70/100 ns

Single 5 Volts ±10% Power Supply

Easy Memory Expansion Using

and

Inputs

Common Data I/O

Three-State Outputs

Fully TTL Compatible Inputs and Outputs

Advanced CMOS Technology

Automatic Power Down

Packages

—32-Pin 600 mil Plastic and Ceramic DIP

—32-Pin 445 mil SOP

—32-Pin TSOP II

DESCRIPTION

The P4C1048L is a 4 Megabit low power CMOS static

RAM organized as 512K x 8. The CMOS memory re-

quires no clocks or refreshing, and has equal access

and cycle times. Inputs are fully TTL-compatible. The

RAM operates from a single 5V±10% tolerance power

supply.

Access times as fast as 45 ns are availale. CMOS is

utilized to reduce power consumption to a low level.

The P4C1048L device provides asynchronous opera-

tion with matching access and cycle times. Memory

locations are specified on address pins A

to A

. Read-

ing is accomplished by device selection (CE low) and

output enabling (OE) while write enable (WE) remains

HIGH. By presenting the address under these condi-

tions, the data in the addressed memory location is pre-

sented on the data input/output pins. The input/output

pins stay in the HIGH Z state when either

is HIGH or

is LOW.

The P4C1048L is packaged in a 32-pin 445 mil plastic

SOP, 32-pin TSOP II, or 600 mil plastic or ceramic side-

brazed DIP.

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATION

DIP (P600, C10),

SOP (S12), TSOP II (T4)

TOP VIEW

Document #

SRAM129

REV D

Revised July 2007

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