P4C1024L
LOW POWER 128K x 8
CMOS STATIC RAM
FEATURES
V
CC
Current (Commercial/Industrial)
— Operating: 70mA/85mA
— CMOS Standby: 100µA/100µA
Access Times
—55/70 (Commercial or Industrial)
Single 5 Volts ±10% Power Supply
Easy Memory Expansion Using
CE
1,
CE
2
and
OE
Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
—32-Pin 600 mil Plastic and Ceramic DIP
—32-Pin 445 mil SOP
—32-Pin TSOP
DESCRIPTION
The P4C1024L is a 1,048,576-bit low power CMOS static
RAM organized as 128Kx8. The CMOS memory re-
quires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
Access times of 55 ns and 70 ns are availale. CMOS is
utilized to reduce power consumption to a low level.
The P4C1024L device provides asynchronous opera-
tion with matching access and cycle times. Memory
locations are specified on address pins A
0
to A
16
. Read-
ing is accomplished by device selection (CE
1
low and
CE
2
high) and output enabling (OE) while write enable
(WE) remains HIGH. By presenting the address under
these conditions, the data in the addressed memory lo-
cation is presented on the data input/output pins. The
input/output pins stay in the HIGH Z state when either
CE
1
or
OE
is HIGH or
WE
or CE
2
is LOW.
The P4C1024L is packaged in a 32-pin TSOP, 445 mil
SOP, and a 600 mil PDIP.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
DIP (P600, C10), SOP (S12)
TOP VIEW
See end of datasheet for TSOP pin configuration.
Document #
SRAM125
REV C
Revised September 2006
1
P4C1024L
RECOMMENDED OPERATING TEMPERATURE & SUPPLY VOLTAGE
Temperature Range (Ambient)
Commercial (0°C to 70°C)
Industrial (-40°C to 85°C)
Supply Voltage
4.5V
≤
V
CC
≤
5.5V
4.5
≤
V
CC
≤
5.5V
MAXIMUM RATINGS
(1)
Stresses greater than those listed can cause permanent damage to the device. These are absolute stress ratings
only. Functional operation of the device is not implied at these or any other conditions in excess of those given in
the operational sections of this data sheet. Exposure to Maximum Ratings for extended periods can adversely
affect device reliability.
Symbol
V
CC
V
TERM
T
A
S
TG
I
OUT
I
LAT
Parameter
Supply Voltage with Respect to GND
Terminal Voltage with Respect to GND (up to 7.0V)
Operating Ambient Temperature
Storage Temperature
Output Current into Low Outputs
Latch-up Current
>200
Min
-0.5
-0.5
-55
-65
Max
7.0
V
CC
+ 0.5
125
150
25
Unit
V
V
°C
°C
mA
mA
DC ELECTRICAL CHARACTERISTICS
(Over Recommended Operating Temperature & Supply Voltage)
(2)
Symbol
V
OH
V
OL
V
IH
V
IL
I
LI
I
LO
I
SB
Parameter
Output High Voltage
(I/O
0
- I/O
7
)
Output Low Voltage
(I/O
0
- I/O
7
)
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage Current
V
CC
Current
TTL Standby Current
(TTL Input Levels)
V
CC
Current
CMOS Standby Current
(CMOS Input Levels)
GND
≤
V
IN
≤
V
CC
GND
≤
V
OUT
≤
V
CC
CE
1
≥
V
IH
or CE
2
≤
V
IL
V
CC
= 5.5V, I
OUT
= 0 mA
CE
1
= V
IH
or CE
2
= V
IL
V
CC
= 5.5V, I
OUT
= 0 mA
CE
1
≥
V
CC
-0.2V, CE
2
≤
0.2V
Ind'l.
Com'l.
Ind'l.
Com'l.
Test Conditions
I
OH
= –1mA, V
CC
= 4.5V
I
OL
= 2.1mA
2.2
-0.5
-5
-2
-5
-2
Min
2.4
0.4
V
CC
+ 0.3
0.8
+5
+2
+5
+2
3
Max
Unit
V
V
V
V
µA
µA
mA
I
SB1
100
µA
Document #
SRAM125
REV C
Page 2 of 10
P4C1024L
CAPACITANCES
(4)
(V
CC
= 5.0V, T
A
= 25°C, f = 1.0 MHz)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Test Conditions
V
IN
= 0V
V
OUT
= 0V
Max
7
9
Unit
pF
pF
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol
I
CC
Parameter
Dynamic Operating Current
Temperature
Range
Commercial
Industrial
*
-55
70
85
-70
70
85
-55
15
25
**
-70
15
25
Unit
mA
mA
*Tested
with outputs open and all address and data inputs changing at the maximum write-cycle rate.
The device is continuously enabled for writing, i.e., CE
2
≥
V
IH
(min),
CE
1
and
WE
≤
V
IL
(max),
OE
is high. Switching
inputs are 0V and 3V.
**As above but @ f=1 MHz and V
IL
/ V
IH
= 0V/ V
CC
.
AC ELECTRICAL CHARACTERISTICS - READ CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
Symbol
t
RC
t
AA
t
AC
t
OH
t
LZ
t
HZ
t
OE
t
OLZ
t
OHZ
t
PU
t
PD
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access
Time
Output Hold from
Address Change
Chip Enable to
Output in Low Z
Chip Disable to
Output in High Z
Output Enable Low
to Data Valid
Output Enable Low to
Low Z
Output Enable High
to High Z
Chip Enable to Power
Up Time
Chip Disable to
Power Down Time
0
55
5
20
0
70
-55
Min
55
55
55
5
10
20
30
5
25
5
10
25
35
Max
Min
70
70
70
-70
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Document #
SRAM125
REV C
Page 3 of 10
P4C1024L
READ CYCLE NO. 1 (OE CONTROLLED)
(1)
OE
READ CYCLE NO. 2 (ADDRESS CONTROLLED)
READ CYCLE NO. 3 (CE CONTROLLED)
CE
Notes:
1.
WE
is HIGH for READ cycle.
2.
CE
1
and
OE
is LOW, and CE
2
is HIGH for READ cycle.
3. ADDRESS must be valid prior to, or coincident with later of
CE
1
transition LOW or CE
2
transition HIGH.
4. Transition is measured ± 200 mV from steady state voltage prior
to change, with loading as specified in Figure 1. This parameter
is sampled and not 100% tested.
5. READ Cycle Time is measured from the last valid address to the
first transitioning address.
Document #
SRAM125
REV C
Page 4 of 10
P4C1024L
AC CHARACTERISTICS - WRITE CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
Symbol
t
WC
t
CW
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
OW
Parameter
Write Cycle Time
Chip Enable Time
to End of Write
Address Valid to
End of Write
Address Set-up
Time
Write Pulse Width
Address Hold
Time
Data Valid to End
of Write
Data Hold Time
Write Enable to
Output in High Z
Output Active from
End of Write
5
-55
Min
55
50
50
0
40
0
25
0
25
5
Max
Min
70
60
60
0
50
0
30
0
30
-70
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WRITE CYCLE NO. 1 (WE CONTROLLED)
(6)
WE
Notes:
6.
CE
1
and
WE
are LOW and CE
2
is HIGH for WRITE cycle.
7.
OE
is LOW for this WRITE cycle to show twz and tow.
8. If
CE
1
goes HIGH or CE
2
goes LOW simultaneously with
WE
HIGH, the output remains in a high impedance state.
9. Write Cycle Time is measured from the last valid address to the first transitioning address.
Document #
SRAM125
REV C
Page 5 of 10
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