PACE1757M/ME
COMPLETE EMBEDDED CPU SUBSYSTEM
FEATURES
Implements complete MIL-STD-1750A ISA including
optional MMU, MFSR, and BPU functions.
Two throughput options:
P1757M 2.5MIPS USAF Dais Mix (Inc.Flt.Pt.)@40 MHz
P1757ME 3.6MIPS USAF Dais Mix (Inc.Flt.Pt.)@40 MHz
Programmable memory and I/O data wait
state generation permits up to four different
memory speeds in the same system.
Programmable address wait states.
Sixteen levels of interrupts are provided per
MIL-STD-1750A. Interrupts can be either
edge- or level-sensitive.
Fault detection and handling
Programmable detection of unimplemented
memory or illegal I/O addresses.
Full implementation of MIL-STD-1750A fault
register.
External address error detection.
Testability and diagnostics.
First falling address and data registers.
Built in test - runs automatically at power on
and after each reset. All hardware blocks
and external busses examined. Hardware
pass/fail for catastrophic failures. Status
register indicates failed test.
Console operating mode which allows
operator to examine and change contents of
registers within the CPU, any system
memory location, or the I/O subsystems.
Single 144-pin Quad straight lead or Gullwing
1.5 square inches of board surface.
Operating temperature range -55 to +125°C;
single 5V ± 10% V
CC
power supply; power
dissipation < 1.9W (worst case at 40 MHz).
All MIL-STD-1750A data formats and address
types implemented.
P1757ME includes additional matrix and vector
instructions to enhance throughput in
navigation, DSP transcendental and other
complex alorithms.
Error detection and correction and parity bit
provided.
Separate high drive external address & data
busses.
10MHz data rate at 40MHz CPU clock
System support functions included:
Arbitrator for use in tightly coupled
multiprocessor design. Bus control provided
to aid in implementation of multi-processor
systems.
MIL-STD-1750A timers A & B, programmable
watch dog timer and programmable bus time-
out function.
Start up ROM support per MIL-STD-1750A.
DMA support for logical and physical memory
addresses.
GENERAL DESCRIPTION
All functions required for a complete MIL-STD-1750A
embedded CPU subsystem are in this single VLSI
microcircuit occupying 1.5 square inches of board space
with less than 1.9 watts of power dissipation at 40 MHz.
Pyramid's P1757M/ME is a complete, single package, 3.6
MIPS subsystem solution to embedded processor
requirements.
The PACE 1757M uses the application-proven PACE
1750A microprocessor, the PACE 1753, and the PACE
1754. The PACE1757ME uses the enhanced PACE
1750AE microprocessor, which has additional instructions
that provide high throughput for transcendental functions,
navigational algorithms, and DSP functions. The PACE
1750AE is an architectural enhancement of the PACE
1750A.
Document #
MICRO-10
REV B
Revised August 2005
PACE 1757 M/ME
DC ELECTRICAL SPECIFICATIONS (Continued)
(Over recommended operating conditions)
Symbol
Parameter
Input LOW current except IB
0
-IB
15
, EDC
0
-
I
IL
EDC
5
,
BUS BUSY
,
BUS LOCK
,
EXT ADR
0
-EXT ADR
7
, TEST ON
Input LOW current TEST ON
Input LOW current IB
0
-IB
15
, EDC
0
-EDC
5
,
BUS BUSY
,
BUS LOCK
,
EXT ADR
0
-EXT ADR
7
Output 3-state current Except SINGERR,
STRBA
Output 3-state current SINGERR, STRBA
Output 3-state current Except
STRBD
Output 3-state current
STRBD
I
CCQC
Quiescent Power Supply Current
(CMOS Input Levels)
80
mA
-500
-50
µA
V
IN
=V
CC
V
CC
=Max
Min
Typ.
Max
-10
Unit
µA
Conditions
V
IN
=GND
V
CC
=Max
I
OZH
50
500
-50
-500
V
OUT
=2.4V
µA
V
CC
=Max
V
OUT
=0.5V
V
CC
=Max
V
IN
< 0.2V or
> V
CC
-0.2V, f=0Hz
Outputs open
V
CC
=Max
I
OZL
µA
I
CCQT
Quiescent Power Supply Current
(TTL Levels)
210
V
IN
=3.4V, All inputs,
f=0Hz
mA
Outputs open
V
CC
=Max
V
IN
< 0.8V or > 3.4V,
Outputs open
mA V =Max
CC
I
CCD
TTL
Dynamic Power Supply Current
f=20 MHz
f=30 MHz
f=35 MHz
f=40 MHz
f=20 MHz
f=30 MHz
f=35 MHz
f=40 MHz
280
310
325
340
150
180
195
210
-25
5
9
I
CCD
Dynamic Power Supply Current
V
IN
< 0.2V or
mA
> V
CC
-0.2V
Outputs open,
V
CC
=Max
V
OUT
=GND
V
CC
=Max
Inputs Only
Outputs (includes I/O
Buffers)
I
OS
C
IN
C
OUT
Output Short Circuit Current
1
(one output shorted at a time)
Input Capacitance
3
Output Capacitance
3
mA
pF
pF
Note 1: Duration of the short should not exceed one second.
Note 2: V
IL
=-3.0V for pulse widths less than or equal to 20ns.
Note 3: This parameter is set by design and not tested.
Document #
MICRO-10
REV B
Page 4 of 34
PACE 1757 M/ME
TIMING GENERATOR STATE DIAGRAMS
Two separate and almost independent state diagrams
may be used to describe the PACE1757M machine
cycle.
The Execution Unit performs according to a cycle of
three state represented by Diagram A (the A machine)
and the External Bus Unit follows a minimum cycle of
four states, indicated in Diagram B (the B machine).
Referring to Diagram A, the paths are defined as
follows for the Execution Unit:
(0) External Reset true
(1) External Reset false
(2) ALU wait or Bus wait.
(3) ALU Branch false
(4) ALU Branch true
Diagram A
Diagram B defines the paths for the External Bus as
follows:
(0) External Reset false
(8) Bus Req. false
(9) Bus Req. true and Bus Av. true
(10) Bus Req. true and Bus Av. false
(11) Bus Av. false
(12) Bus Av. true
(13) RDYA false
(14) RDYA true
(16) RDYD false
(17) RDYD true and Bus Req. true and Bus Av. true
(18) RDYD true and Bus Req. false
(19) RDYD true and Bus Req. true and Bus Av. false
(20) Bus Req. true and Bus Av. true
Diagram B
NOTE:
Bus A
V
= Bus grant and Bus not busy and Bus not locked.
Document #
MICRO-10
REV B
Page 5 of 34
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