CY7C68013-56PVCT datasheet, PDF

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CY7C68013-56PVCT: DescriptionMicrocontroller, 8-Bit, EEPROM, 48MHz, CMOS, PDSO56, SSOP-56; CategoryThe embedded processor and controller Microcontrollers and processors; File Size531KB，52 Pages; ManufacturerCypress Semiconductor

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CY7C68013-56PVCT Overview

Microcontroller, 8-Bit, EEPROM, 48MHz, CMOS, PDSO56, SSOP-56

CY7C68013-56PVCT Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Cypress Semiconductor
Parts packaging code	SSOP
package instruction	SSOP,
Contacts	56
Reach Compliance Code	unknown
Is Samacsys	N
Has ADC	NO
Address bus width	16
bit size	8
maximum clock frequency	24 MHz
DAC channel	NO
DMA channel	NO
External data bus width	8
JESD-30 code	R-PDSO-G56
JESD-609 code	e0
length	18.796 mm
Humidity sensitivity level	1
Number of I/O lines	40
Number of terminals	56
Maximum operating temperature	70 °C
Minimum operating temperature
PWM channel	NO
Package body material	PLASTIC/EPOXY
encapsulated code	SSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	220
Certification status	Not Qualified
ROM programmability	EEPROM
Maximum seat height	2.794 mm
speed	48 MHz
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	0.635 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.5057 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER
Base Number Matches	1

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CY7C68013

EZ-USB FX2™ USB Microcontroller

High-speed USB Peripheral Controller

Cypress Semiconductor Corporation

Document #: 38-08012 Rev. *C

•

3901 North First Street

•

San Jose

CA 95134

•

408-943-2600

Revised December 19, 2002

CY7C68013

TABLE OF CONTENTS

1.0 EZ-USB FX2™ FEATURES ............................................................................................................. 6

2.0 APPLICATIONS ............................................................................................................................... 7

3.0 FUNCTIONAL OVERVIEW .............................................................................................................. 7

3.1 USB Signaling Speed ................................................................................................................. 7

3.2 8051 Microprocessor .................................................................................................................. 7

3.3 I

C-compatible Bus ..................................................................................................................... 8

3.4 Buses .......................................................................................................................................... 8

3.5 USB Boot Methods ..................................................................................................................... 9

3.6 ReNumeration™ ......................................................................................................................... 9

3.7 Bus Powered Applications .......................................................................................................... 9

3.8 Interrupt System ........................................................................................................................ 10

3.9 Reset and Wakeup ................................................................................................................... 11

3.10 Program/Data RAM ................................................................................................................. 11

3.11 Register Addresses ................................................................................................................. 14

3.12 Endpoint RAM ......................................................................................................................... 14

3.13 External FIFO interface ........................................................................................................... 16

3.14 GPIF ........................................................................................................................................ 16

3.15 USB Uploads and Downloads ................................................................................................. 17

3.16 Autopointer Access ................................................................................................................. 17

3.17 I

C-compatible Controller ........................................................................................................ 17

4.0 PIN ASSIGNMENTS ...................................................................................................................... 18

4.1 CY7C68013 Pin Descriptions ................................................................................................... 24

5.0 REGISTER SUMMARY .................................................................................................................. 31

6.0 ABSOLUTE MAXIMUM RATINGS ................................................................................................ 37

7.0 OPERATING CONDITIONS ........................................................................................................... 37

8.0 DC CHARACTERISTICS ............................................................................................................... 37

8.1 USB Transceiver ....................................................................................................................... 37

9.0 AC ELECTRICAL CHARACTERISTICS ....................................................................................... 38

9.1 USB Transceiver ....................................................................................................................... 38

9.2 Program Memory Read ............................................................................................................. 38

9.3 Data Memory Read ................................................................................................................... 39

9.4 Data Memory Write ................................................................................................................... 40

9.5 GPIF Synchronous Signals ....................................................................................................... 41

9.6 Slave FIFO Synchronous Read ................................................................................................ 42

9.7 Slave FIFO Asynchronous Read .............................................................................................. 43

9.8 Slave FIFO Synchronous Write ................................................................................................ 43

9.9 Slave FIFO Asynchronous Write ............................................................................................... 44

9.10 Slave FIFO Synchronous Packet End Strobe ......................................................................... 44

9.11 Slave FIFO Asynchronous Packet End Strobe ....................................................................... 45

9.12 Slave FIFO Output Enable ...................................................................................................... 45

9.13 Slave FIFO Address to Flags/Data ......................................................................................... 45

9.14 Slave FIFO Synchronous Address .......................................................................................... 46

9.15 Slave FIFO Asynchronous Address ........................................................................................ 46

Document #: 38-08012 Rev. *C

Page 2 of 52

CY7C68013

LIST OF FIGURES

Figure 1-1. Block Diagram ....................................................................................................................... 6

Figure 3-1. Internal Code Memory, EA = 0 ............................................................................................ 12

Figure 3-2. External Code Memory, EA = 1........................................................................................... 13

Figure 3-3. Endpoint Configuration ........................................................................................................ 15

Figure 4-1. Signals................................................................................................................................. 19

Figure 4-2. CY7C68013 128-pin TQFP Pin Assignment ....................................................................... 20

Figure 4-3. CY7C68013 100-pin TQFP Pin Assignment ....................................................................... 21

Figure 4-4. CY7C68013 56-pin SSOP Pin Assignment ......................................................................... 22

Figure 4-5. CY7C68013 56-pin QFN Pin Assignment ........................................................................... 23

Figure 9-1. Program Memory Read Timing Diagram............................................................................. 38

Figure 9-2. Data Memory Read Timing Diagram ................................................................................... 39

Figure 9-3. Data Memory Write Timing Diagram ................................................................................... 40

Figure 9-4. GPIF Synchronous Signals Timing Diagram ....................................................................... 41

Figure 9-5. Slave FIFO Synchronous Read Timing Diagram ................................................................ 42

Figure 9-6. Slave FIFO Asynchronous Read Timing Diagram .............................................................. 43

Figure 9-7. Slave FIFO Synchronous Write Timing Diagram ................................................................ 43

Figure 9-8. Slave FIFO Asynchronous Write Timing Diagram............................................................... 44

Figure 9-9. Slave FIFO Synchronous Packet End Strobe Timing Diagram ........................................... 44

Figure 9-10. Slave FIFO Asynchronous Packet End Strobe Timing Diagram ....................................... 45

Figure 9-11. Slave FIFO Output Enable Timing Diagram ...................................................................... 45

Figure 9-12. Slave FIFO Address to Flags/Data Timing Diagram ......................................................... 45

Figure 9-13. Slave FIFO Synchronous Address Timing Diagram.......................................................... 46

Figure 9-14. Slave FIFO Asynchronous Address Timing Diagram ........................................................ 46

Figure 11-1. 56-lead Shrunk Small Outline Package O56 ..................................................................... 47

Figure 11-2. 56-lead Quad Flatpack No Lead Package (8 × 8 mm) LF56............................................. 47

Figure 11-3. 100-Pin Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm) A101 ......................................... 48

Figure 11-4. 128-Lead Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm) A128 ...................................... 49

Figure 13-1. Cross-section of the Area Underneath the QFN Package ................................................ 50

Figure 13-2. Plot of the Solder Mask (White Area) ................................................................................ 50

Figure 13-3. X-ray image of the assembly ............................................................................................. 51

Document #: 38-08012 Rev. *C

Page 4 of 52

CY7C68013

LIST OF TABLES

Table 3-1. Special Function Registers .................................................................................................... 9

Table 3-2. Default ID Values for FX2 ...................................................................................................... 9

Table 3-3. INT2 USB Interrupts ............................................................................................................ 10

Table 3-4. Individual FIFO/GPIF Interrupt Sources .............................................................................. 11

Table 3-5. Default Full-Speed Alternate Settings ................................................................................. 15

Table 3-6. Default High-Speed Alternate Settings ................................................................................ 16

Table 3-7. Strap Boot EEPROM Address Lines to These Values ........................................................ 18

Table 4-1. FX2 Pin Descriptions ........................................................................................................... 24

Table 5-1. FX2 Register Summary ....................................................................................................... 31

Table 8-1. DC Characteristics ............................................................................................................... 37

Table 9-1. Program Memory Read Parameters .................................................................................... 38

Table 9-2. Data Memory Read Parameters .......................................................................................... 39

Table 9-3. Data Memory Write Parameters .......................................................................................... 40

Table 9-4. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK ............................. 41

Table 9-5. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK ............................ 41

Table 9-6. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK ....................... 42

Table 9-7. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK ..................... 42

Table 9-8. Slave FIFO Asynchronous Read Parameters ..................................................................... 43

Table 9-9. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK ....................... 43

Table 9-10. Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK .................... 44

Table 9-11. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK ................... 44

Table 9-12. Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK 44

Table 9-13. Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK 45

Table 9-14. Slave FIFO Asynchronous Packet End Strobe Parameters .............................................. 45

Table 9-15. Slave FIFO Output Enable Parameters ............................................................................. 45

Table 9-16. Slave FIFO Address to Flags/Data Parameters ................................................................ 46

Table 9-17. Slave FIFO Synchronous Address Parameters ................................................................. 46

Table 9-18. Slave FIFO Asynchronous Address Parameters ............................................................... 46

Table 10-1. Ordering Information .......................................................................................................... 46

Document #: 38-08012 Rev. *C

Page 5 of 52

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