M
Part
Number
24AA64
24LC64
†
100
24AA64/24LC64
PACKAGE TYPE
Temp
Ranges
I
I, E
A2
Vss
3
4
64K I
2
C
™
CMOS Serial EEPROM
DEVICE SELECTION TABLE
Vcc
Range
1.8-5.5V
2.5-5.5V
Max Clock
Frequency
400 kHz
†
400
kHz
‡
PDIP
A0
A1
1
8
Vcc
WP
SCL
SDA
24xx64
2
7
6
5
kHz for Vcc < 2.5V.
‡
100 kHz for E temperature range.
FEATURES
• Low power CMOS technology
- Maximum write current 3 mA at 5.5V
- Maximum read current 400
µ
A at 5.5V
- Standby current 100 nA typical at 5.5V
• 2-wire serial interface bus, I
2
C compatible
• Cascadable for up to eight devices
• Self-timed ERASE/WRITE cycle
• 32-byte page or byte write modes available
• 5 ms max write cycle time
• Hardware write protect for entire array
• Output slope control to eliminate ground bounce
• Schmitt trigger inputs for noise suppression
• 1,000,000 erase/write cycles guaranteed
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• 8-pin PDIP, SOIC (150 and 208 mil) and TSSOP
packages; 14-pin SOIC package
• Temperature ranges:
- Industrial (I):
-40
°
C to +85
°
C
- Automotive (E)
-40
°
C to +125
°
C
SOIC
A0
A1
A2
V
SS
1
8
V
CC
WP
SCL
SDA
24xx64
2
3
4
7
6
5
TSSOP
WP
Vcc
A0
A1
1
2
3
4
8
7
6
5
SCL
SDA
Vss
A2
24xx64
BLOCK DIAGRAM
A0…A2
WP
HV GENERATOR
DESCRIPTION
The Microchip Technology Inc. 24AA64/24LC64
(24xx64*) is a 8K x 8 (64K bit) Serial Electrically Eras-
able PROM capable of operation across a broad volt-
age range (1.8V to 5.5V). It has been developed for
advanced, low power applications such as personal
communications or data acquisition. This device also
has a page-write capability of up to 32 bytes of data.
This device is capable of both random and sequential
reads up to the 64K boundary. Functional address lines
allow up to eight devices on the same bus, for up to 512
Kbits address space. This device is available in the
standard 8-pin plastic DIP, 8-pin SOIC (150 and
208 mil), and 8-pin TSSOP.
I/O
CONTROL
LOGIC
MEMORY
CONTROL
LOGIC
XDEC
EEPROM
ARRAY
PAGE LATCHES
I/O
SCL
YDEC
SDA
V
CC
V
SS
SENSE AMP
R/W CONTROL
I
2
C is a trademark of Philips Corporation.
*24xx64 is used in this document as a generic part number for the 24AA64/24LC64 devices.
©
1998 Microchip Technology Inc.
DS21189B-page 1
24AA64/24LC64
1.0
1.1
ELECTRICAL
CHARACTERISTICS
Maximum Ratings*
TABLE 1-1
Name
A0,A1,A2
V
SS
SDA
SCL
WP
V
CC
PIN FUNCTION TABLE
Function
User Configurable Chip Selects
Ground
Serial Data
Serial Clock
Write Protect Input
+1.8 to 5.5V (24AA64)
+2.5 to 5.5V (24LC64)
Vcc .................................................................................................7.0V
All inputs and outputs w.r.t. Vss............................... -0.6V to Vcc +1.0V
Storage temperature ................................................... -65˚C to +150˚C
Ambient temp. with power applied............................... -65˚C to +125˚C
Soldering temperature of leads (10 seconds) ........................... +300˚C
ESD protection on all pins...........................................................
≥
4 kV
*Notice: Stresses above those listed under “Maximum Ratings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for extended peri-
ods may affect device reliability.
TABLE 1-2
DC CHARACTERISTICS
Industrial (I):
V
CC
= +1.8V to 5.5V
Automotive (E): V
CC
= 4.5V to 5.5V
Symbol
Min
Max
Tamb = -40
°
C to +85
°
C
Tamb = -40
°
C to 125
°
C
Units
Conditions
All parameters apply across the
recommended operating ranges
unless otherwise noted.
Parameter
A0, A1, A2,
SCL, SDA, and WP pins:
High level input voltage
Low level input voltage
Hysteresis of Schmitt Trigger
inputs (SDA, SCL pins)
Low level output voltage
Input leakage current
Output leakage current
Pin capacitance
(all inputs/outputs)
Operating current
Standby current
V
IH
V
IL
V
HYS
V
OL
I
LI
I
LO
C
IN
, C
OUT
I
CC
Write
I
CC
Read
I
CCS
0.7 V
CC
—
0.05 V
CC
—
-10
-10
—
—
—
—
—
0.3 V
CC
0.2 V
CC
—
0.40
10
10
10
3
400
1
V
V
V
V
V
µ
A
µ
A
pF
mA
µ
A
µ
A
V
CC
≥
2.5V
V
CC
< 2.5V
V
CC
> 2.5V (Note)
I
OL
= 3.0 mA @ V
CC
= 4.5V
I
OL
= 2.1 mA @ V
CC
= 2.5V
V
IN
= Vss to V
CC
, WP = V
SS
V
IN
= Vss or V
CC
, WP = V
CC
V
OUT
= Vss to V
CC
V
CC
= 5.0V (Note)
Tamb = 25˚C, f
c
= 1 MHz
V
CC
= 5.5V
V
CC
= 5.5V, SCL = 400 kHz
SCL = SDA = V
CC
= 5.5V
A0, A1, A2, WP = V
SS
Note:
This parameter is periodically sampled and not 100% tested.
FIGURE 1-1:
BUS TIMING DATA
T
F
T
HIGH
V
HYS
T
R
SCL
T
SU
:
STA
T
LOW
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
SDA
IN
T
HD
:
STA
T
SP
T
AA
T
BUF
SDA
OUT
WP
(protected)
(unprotected)
T
SU
:
WP
T
HD
:
WP
DS21189B-page 2
©
1998 Microchip Technology Inc.
24AA64/24LC64
TABLE 1-3
AC CHARACTERISTICS
Tamb = -40
°
C to +85
°
C
Tamb = -40
°
C to 125
°
C
Conditions
4.5V
≤
V
CC
≤
5.5V (E Temp range)
1.8V
≤
V
CC
≤
2.5V
2.5V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V (E Temp range)
1.8V
≤
V
CC
≤
2.5V
2.5V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V (E Temp range)
1.8V
≤
V
CC
≤
2.5V
2.5V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V (E Temp range)
1.8V
≤
V
CC
≤
2.5V
2.5V
≤
V
CC
≤
5.5V
(Note 1)
4.5V
≤
V
CC
≤
5.5V (E Temp range)
1.8V
≤
V
CC
≤
2.5V
2.5V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V (E Temp range)
1.8V
≤
V
CC
≤
2.5V
2.5V
≤
V
CC
≤
5.5V
(Note 2)
4.5V
≤
V
CC
≤
5.5V (E Temp range)
1.8V
≤
V
CC
≤
2.5V
2.5V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V (E Temp range)
1.8V
≤
V
CC
≤
2.5V
2.5V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V (E Temp range)
1.8V
≤
V
CC
≤
2.5V
2.5V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V (E Temp range)
1.8V
≤
V
CC
≤
2.5V
2.5V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V (E Temp range)
1.8V
≤
V
CC
≤
2.5V
2.5V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V (E Temp range)
1.8V
≤
V
CC
≤
2.5V
2.5V
≤
V
CC
≤
5.5V
C
B
≤
100 pF (Note 1)
(Notes 1 and 3)
All parameters apply across the spec-
Industrial (I):
V
CC
= +1.8V to 5.5V
ified operating ranges unless other-
Automotive (E): V
CC
= +4.5V to 5.5V
wise noted.
Parameter
Clock frequency
Symbol
F
CLK
Min
—
—
—
4000
4000
600
4700
4700
1300
—
—
—
—
4000
4000
600
4700
4700
600
0
250
250
100
4000
4000
600
4000
4000
600
4700
4000
1300
—
—
—
4700
4700
1300
10
—
—
1M
Max
100
100
400
—
—
—
—
—
—
1000
1000
300
300
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3500
3500
900
—
—
—
250
50
5
—
Units
kHz
Clock high time
T
HIGH
ns
Clock low time
T
LOW
ns
SDA and SCL rise time
(Note 1)
SDA and SCL fall time
START condition hold time
T
R
ns
T
F
T
HD
:
STA
ns
ns
START condition setup time
T
SU
:
STA
ns
Data input hold time
Data input setup time
T
HD
:
DAT
T
SU
:
DAT
ns
ns
STOP condition setup time
T
SU
:
STO
ns
WP setup time
T
SU
:
WP
ns
WP hold time
T
HD
:
WP
ns
Output valid from clock
(Note 2)
Bus free time: Time the bus must be
free before a new transmission can
start
Output fall time from V
IH
minimum to V
IL
maximum
Input filter spike suppression
(SDA and SCL pins)
Write cycle time (byte or page)
Endurance
Note 1:
2:
3:
4:
T
AA
ns
T
BUF
ns
T
OF
T
SP
T
WC
ns
ns
ms
cycles
25°C, V
CC
= 5.0V, Block Mode (Note 4)
Not 100% tested. C
B
= total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
The combined T
SP
and V
HYS
specifications are due to new Schmitt trigger inputs which provide improved noise spike
suppression. This eliminates the need for a TI specification for standard operation.
This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please
consult the Total Endurance Model which can be obtained on Microchip’s BBS or website.
©
1998 Microchip Technology Inc.
DS21189B-page 3
24AA64/24LC64
2.0
2.1
PIN DESCRIPTIONS
A0, A1, A2 Chip Address Inputs
4.0
BUS CHARACTERISTICS
The following
bus protocol
has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
The A0,A1,A2 inputs are used by the 24xx64 for multi-
ple device operation. The levels on these inputs are
compared with the corresponding bits in the slave
address. The chip is selected if the compare is true.
Up to eight devices may be connected to the same bus
by using different chip select bit combinations. These
inputs must be connected to either V
CC
or V
SS
.
2.2
SDA Serial Data
4.1
Bus not Busy (A)
This is a bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open-
drain terminal, therefore, the SDA bus requires a pullup
resistor to V
CC
(typical 10 kΩ for 100 kHz, 2 kΩ for
400 kHz)
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions.
Both data and clock lines remain HIGH.
4.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START condi-
tion.
4.3
Stop Data Transfer (C)
2.3
SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must end with a STOP condition.
4.4
Data Valid (D)
2.4
WP
This pin can be connected to either Vss, Vcc or left
floating. An internal pull-down resistor on this pin will
keep the device in the unprotected state if left floating.
If tied to Vss or left floating, normal memory operation
is enabled (read/write the entire memory 0000-1FFF).
If tied to V
CC
, WRITE operations are inhibited. Read
operations are not affected.
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device.
3.0
FUNCTIONAL DESCRIPTION
The 24xx64 supports a bi-directional two-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device
receiving data as a receiver. The bus must be con-
trolled by a master device which generates the serial
clock (SCL), controls the bus access, and generates
the START and STOP conditions while the 24xx64
works as a slave. Both master and slave can operate as
a transmitter or receiver but the master device deter-
mines which mode is activated.
4.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this acknowledge
bit.
Note:
The 24xx64 does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable LOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. Dur-
ing reads, a master must signal an end of data to the
slave by NOT generating an acknowledge bit on the
last byte that has been clocked out of the slave. In this
case, the slave (24xx64) will leave the data line HIGH
to enable the master to generate the STOP condition.
©
1998 Microchip Technology Inc.
DS21189B-page 4
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