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DTC-19300
LVDT/RVDT-TO-DIGITAL CONVERTER
FEATURES
•
Internal Oscillator:
Programmable for Voltage and
Frequency
•
Programmable Signal Gain
•
Programmable for 12- or14-Bit
Resolution
•
Velocity Output
•
Built-In-Test Output
•
Three-State, Two-Byte Digital Output
DESCRIPTION
The DTC-19300 is a 12- or 14-bit LVDT (Linear Variable Differential
Transformer)- or RVDT (Rotary Variable Differential Transformer)-to- digital
converter which also supplies the AC excitation to drive the LVDT. Internal AC
excitation voltage, frequency, signal gain and resolution are all programma-
ble for optimum system performance. Packaged in a 36-pin hybrid, the DTC-
19300 also features Velocity (VEL) and Built-In-Test (BIT) outputs. The three-
state digital outputs are provided in a two byte format, for easy computer
interface.
The DTC-19300 has been designed precisely for use with an LVDT. Inherent
characteristics of the DTC-19300, such as the input to output phase shift,
have been given considerable attention. The converter’s reference voltage is
derived from, and is in phase with, the LVDT output signal. Therefore, any
errors due to the transducer’s phase shift are virtually eliminated. Additionally,
the programmability of the DTC-19300 will accomodate a broad range of
LVDT’s.
APPLICATIONS
The DTC-19300 provides many features previously supplied by individual
system components. Because of its internal AC source, programmable fea-
tures, fault indicator (BIT), and velocity output (VEL), the need for other sys-
tem circuits is minimized. The DTC-19300 is an excellent choice for applica-
tions using the LVDT transducer for position feedback, such as military, com-
mercial aerospace and industrial control systems.
FOR MORE INFORMATION CONTACT:
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
Technical Support:
1-800-DDC-5757 ext. 7771
All trademarks are the property of their respective owners.
©
1998, 1999 Data Device Corporation
10k
R1
35
29
SJ
SO
Data Device Corporation
www.ddc-web.com
10k
R5
PHASE
COMP
C2
DTC-19300
18
BIT
REFERENCE
CONDITIONER
BIT
DETECT
ZERO SET
TIMING
26
VEL
LVDT
FULL
SCALE
R2
34 SG
-
+
REF
SUM
(REF)
14 BIT BRIDGE
TRANSPARENT
LATCH
1 LSB ANTILITTER
FEEDBACK
ERROR
AMP
PROG
GAIN
AMP
DIFF
HIGH
ACCURACY
RATIO BRIDGE
DEMOD
SIG
ERROR
PROCESSOR
VCO
U
T
33 S
DIF
GAIN
32 R
24
2
U
14 BIT
U-D COUNTER
T
U/D
INH
14 BIT OUTPUT
TRANSPARENT
LATCH
POWER
OSCILLATOR
3 STATE
TTL BUFFER
3 STATE
TTL BUFFER
e
25
V
31 RO
36 RI
50 ns DELAY
23
A
INHIBIT
C1
Q
TRANSPARENT
LATCH
17
INH
30
19 OSC
+
21
+5 V
27
INTERNAL
DC REF (11V)
FREQ
R4 22
RM
20
1
EM
BITS 1-6
BITS 7-14
POWER
SUPPLY
CONDITIONER
16
EL
+15 V
AMPL
R3
DTC-19300
J-06/05-0
FIGURE 1. DTC-19300 BLOCK DIAGRAM
TABLE 1. DTC-19300 SPECIFICATIONS
Specifications apply over temperature and power supply ranges
PARAMETER
RESOLUTION
ACCURACY
REPEATABILITY
DIFFERENTIAL
LINEARITY
FREQUENCY OUT
(OSC Pin 18)
Frequency
Voltage
Current Drive
Protection
REFERENCE IN (RI)
Full Scale Voltage
Input Impedance
VALUE
DESCRIPTION
12 or 14 bits
0.25, 0.05% of Reading
1 LSB max
1 LSB max
Programmable
See Ordering Information.
5 kHz ± 10%
2.7 Vrms ± 20%
Tunable down to 400 Hz; disable with R4 = oo (See
Setting Up and Programming). 20% @ room temp,
add 20% @ overtemp. Scalable down (See Setting
Up and Programming).
20 mA rms min
Short circuit, overcurrent, and voltage transient
protected.
2 Vrms ± 10%
20 MOhms min
Transient protected voltage follower.
REFERENCE IN (R)
Voltage
Input Impedance
1 Vrms ± 10%
20 MOhms min
Transient protected voltage follower.
SIGNAL IN (S)
Full Scale Voltage
Input Impedance
2 Vrms
20 MOhms min
Transient protected voltage follower.
DIGITAL
INPUTS / OUTPUTS
Logic Type
Inputs
Loading
INH (Inhibit)
EM (Enable Bits 1-6)
EL (Enable Bits 7-14)
A (Resolution Control)
OUTPUTS
Parallel Data
BIT (Built-In-Test)
Drive Capability
TTL/CMOS compatible
Logic 0 = 0.8 V max
Logic 1 = 2.0 V min
10 µA max
Pull up current source to +5V//5 pF, CMOS transient
protection.
Logic
Logic
Logic
Logic
0
1
0
1
inhibits, data valid within 0.5 µs.
enables.
enables, data valid within 150 ns.
= high impedance, data high Z within 100 ns.
Logic 1 = 14-bit resolution.
Logic 0 = 12-bit resolution.
12 or 14 bits
Logic 0 = 1 TTL load
Logic 1 = 10 TTL loads
High Z = 10 µA//5 pF max
Bi-Polar two’s compliment.
Bit 1 = MSB; Bit 14 or Bit 12 = LSB.
Logic 0 for BIT condition (converter malfunction).
1.6 mA @ 0.4V max +50 pF.
-0.4V mA at 2.8 V min +50 pF.
When in the third state.
ANALOG OUTPUTS
V (Analog Ground)
VEL (Velocity)
Scaling
Scaling TC
Reversal Error
Linearity
Zero Offset
Noise and Ripple
AC peak/DC Average
Load
5.5 VDC nom
+4V ± 15%
200 PPM / °C max
2 % max
2 % of output max
10 mV max
50 mV rms
0.5 % max
40 kOhms min
VEL is with respect to V.
1 (14-bit) or 4 (12-bit) ranges per second.
Data Device Corporation
www.ddc-web.com
3
DTC-19300
J-06/05-0
TABLE 1. DTC-19300 SPECIFICATIONS (CONT.)
Specifications apply over temperature and power supply ranges
PARAMETER
DYNAMIC
CHARACTERISTICS
Tracking Rate
Bandwidth, Closed Loop
Ka
A1
A2
A
B
Acc for 1 LSB lag
Setting Time - half scale
step
POWER SUPPLIES
+5V SUPPLY
Nominal Voltage and Range
Max Voltage w/o Damage
Current, Peak
Current, Average
+15V SUPPLY
Nominal Voltage and Range
Max Voltage w/o Damage
Current Peak
Current, Average
TEMPERATURE RANGES
Operating, Ambient
-3XX
-1XX
Storage
PHYSICAL
CHARACTERISTICS
Size
Weight
VALUE
DESCRIPTION
1 full range per sec, min
18 Hz
1600 1/sec2
0.4 1/sec
4000 1/sec
40 1/sec
20 1/sec
0.1 full ranges per sec2
150ms
+5 VDC ± 10%
+8 VDC
10 mA max
10 mA max
+15 VDC ±5%
+18 VDC
25 mA max, +√2 x Iosc rms.
35 mA max, + 0.9 x 0.5 x Iosc rms
0°C to +70°C
-55°C to +125°C
-65°C to +150°C
0.78 x 1.9 x 0.21 inches
(20 x 48 x 5.3 mm)
1 oz
(28 gm)
36-pin DDIP
INTRODUCTION
The circuit shown in FIGURE 1 (DTC-19300 Block Diagram)
consists of four main parts:
1. Signal input conditioner
2. Feedback loop (whose elements include a high accuracy ratio
bridge, a demodulator, an error processor, a VCO and an up-
down counter)
3. Power oscillator to excite the LVDT
4. Digital interface circuit (including various latches and buffers)
In the LVDT, position output is transmitted as a differential volt-
age that varies linearly with changes in the core position. The
DTC-19300 receives the differential and sum voltage at its inputs
and internally produces a digital position
δ
which tracks the dif-
ferential position
λ
to within the specified accuracy of the con-
verter.
A high accuracy ratio bridge is used to compute (λ -
δ),
where:
λ
= the LVDT’s core position.
δ
= the digital position contained in the converter’s up-down
counter.
Data Device Corporation
www.ddc-web.com
The tracking process consists of continually adjusting
δ
to make
(λ -
δ)
0, so that
δ
will represent the core’s position,
λ.
The ratio bridge output is fed to a demodulator whose output is
an analog DC level proportional to (λ -
δ).
The error processor
receives its input from the demodulator and integrates the error
signal (λ -
δ)
which then drives a Voltage-Controlled Oscillator
(VCO).
Functionally, the up-down counter is an incremental integrator.
Therefore, there are two stages of integration which make the
converter a type II tracking servo. In a type II servo the VCO
always settles to the counting rate which makes the dδ/dt equal
to dλ/dt without lag. The output data will always be fresh and
available as long as the maximum tracking rate of the converter
is not exceeded.
4
DTC-19300
J-06/05-0
POWER OSCILLATOR
The DTC-19300 contains an internal power oscillator. The OSC
output (pin 19) can be programmed for voltage and frequency.
The default output voltage is 2.7 Vrms, scalable down with an
external resistor R3 connected between RM (pin 20) and V (pin
25). The default frequency is 5 kHz, tunable to 400 Hz with an
external resistor R4 connected between RF1 (pin 21) and RF2
(pin 22). If desired, an external oscillator can be used in place of
the internal oscillator.
SOLID STATE BUFFERED INPUTS
The signal and reference inputs are voltage follower inputs with
high impedance that do not load the LVDT. The maximum tran-
sient peak voltage should not exceed 100 V.
A logic 0 applied to the T input latches data, and a logic 1 applied
to T allows the bits to change. The Inhibit Transparent Latch pre-
vents the transmission of invalid data when there is an overlap
between T (VCO clock to up-down counter) and INH. While the
counter is not being updated, T is at a logic 0 and the Inhibit
Latch is transparent. When T goes to a logic 1, the Inhibit Latch
is locked. If T occurs after INH has been applied, the latch will
remain locked and its data will not change until T returns to logic
0; if INH is applied during T, the latch will not lock until the T pulse
is a logic 0. The purpose of the 50 ns delay is to prevent a race
condition between T and INH where the up-down counter begins
to change as an INH is applied.
FIGURE 2 illustrates the Inhibit Timing. Whenever an input posi-
tion change occurs, the converter changes the digital position in
1 LSB steps and generates a T pulse, delayed by 50 ns, nomi-
nal. Valid data is available at the outputs 0.2 µs after the leading
edge of T. An INH input, regardless of its duration, does not
affect the converter update.
A simple method of interfacing to a computer is:
DIGITAL INTERFACE
The digital interface circuitry has three main functions:
1. Latch the output bits during an Inhibit (INH) command
allowing stable data to be read out of the DTC-19300
2. Furnish parallel tri-state data formats
1. apply INH
3. Act as a buffer between the internal CMOS logic and the
external TTL logic
In the DTC-19300, applying an INHIBIT (INH) command will lock
the data in the Output Transparent Latch without interfering with
the continuous tracking of the feedback loop. Therefore, the dig-
ital position always updates, and the INHIBIT can be applied for
an arbitrary amount of time. The Inhibit Transparent Latch and
the 50 ns delay are part of the inhibit circuitry. For further infor-
mation, see the INHIBIT (INH, PIN 17) paragraph.
2. wait 0.5 µs minimum
3. transfer data and release INH
As long as the converter’s maximum tracking rate is not exceed-
ed, there will be no lag in the converter output. If a step input
occurs, as when power is initially applied, the response will be
critically damped. FIGURE 3 shows the response to a step input.
After initial slewing at the maximum tracking rate of the convert-
er, there is one overshoot (inherent in a type II servo). The over-
shoot settling to final value is a function of the small signal set-
tling to final value.
LOGIC OUTPUT
Logic outputs from the DTC-19300 consist of the LVDT core’s
digital position in 12 or 14 parallel data bits. All logic outputs are
short-circuit proof to ground and +5 V. The internal Timing signal
(T) is a positive, 0.4 to 0.7 µs pulse. Data changes approximate-
ly 50 ns after the leading edge of T, and the position is deter-
mined by the sum of the bits at logic 1. Digital outputs are three-
state and are provided in two bytes: bits 1 through 6 (MSBs)
which are enabled by the signal EM, and bits 7 through 14
(LSBs) which are enabled by the signal EL. Outputs are valid
(logic 1 or 0) 150 ns maximum after setting EM or EL low, and
are high impedance within 100 ns maximum of setting EM or EL
high. Both EM and EL are internally puIled-up to +5 V at 100 nA
maximum .
BUILT-IN-TEST (BIT, PIN 18)
The BIT output monitors the level of the demodulator (D). If D
exceeds approximately 65 bits, the logic level at BIT will change
from logic 1 to logic 0. This condition will occur during a large
step and reset after the converter settles out. BIT will also be set
for an over-velocity condition because the converter loop cannot
maintain input-output sync, or if the converter malfunctions
where it cannot maintain the loop at a null.
INHIBIT (INH, PIN 17)
The INH input locks the Output Transparent Latch (See FIGURE
1) so the bits will remain stable while data is being transferred.
The output is stable 0.5 µs after INH is driven to logic 0.
Data Device Corporation
www.ddc-web.com
5
DTC-19300
J-06/05-0
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