IDT70V639S10BFI datasheet, PDF

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IDT70V639S10BFI: Description128K X 18 DUAL-PORT SRAM, 12 ns, PBGA208; Categorystorage; File Size189KB，23 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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IDT70V639S10BFI Overview

128K X 18 DUAL-PORT SRAM, 12 ns, PBGA208

IDT70V639S10BFI Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	208
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Maximum supply/operating voltage	3.45 V
Minimum supply/operating voltage	3.15 V
Rated supply voltage	3.3 V
maximum access time	12 ns
Processing package description	15 × 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, FPBGA-208
state	ACTIVE
Craftsmanship	CMOS
packaging shape	SQUARE
Package Size	GRID ARRAY, THIN PROFILE, FINE PITCH
surface mount	Yes
Terminal form	BALL
Terminal spacing	0.8000 mm
terminal coating	tin lead
Terminal location	BOTTOM
Packaging Materials	Plastic/Epoxy
Temperature level	INDUSTRIAL
memory width	18
organize	128K × 18
storage density	2.36E6 deg
operating mode	ASYNCHRONOUS
Number of digits	131072 words
Number of digits	128K
Memory IC type	dual-port static random access memory
serial parallel	parallel

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HIGH-SPEED 3.3V 128K x 18

ASYNCHRONOUS DUAL-PORT

STATIC RAM

PRELIMINARY

IDT70V639S

Features

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed access

– Commercial: 10/12/15ns (max.)

– Industrial: 12/15ns (max.)

Dual chip enables allow for depth expansion without

external logic

IDT70V639 easily expands data bus width to 36 bits or

more using the Master/Slave select when cascading more

than one device

M/S = V

for

BUSY

output flag on Master,

M/S = V

for

BUSY

input on Slave

Busy and Interrupt Flags

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

Separate byte controls for multiplexed bus and bus

matching compatibility

Supports JTAG features compliant to IEEE 1149.1

– Due to limited pin count, JTAG is not supported on the

128-pin TQFP package.

LVTTL-compatible, single 3.3V (±150mV) power supply for

core

LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)

power supply for I/Os and control signals on each port

Available in a 128-pin Thin Quad Flatpack, 208-ball fine

pitch Ball Grid Array, and 256-ball Ball Grid Array

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

Functional Block Diagram

R/W

Dout0-8_L

Dout9-17_L

Dout0-8_R

Dout9-17_R

128K x 18

MEMORY

ARRAY

I/O

- I/O

17L

Din_L

Din_R

I/O

- I/O

17R

16L

Address

Decoder

ADDR_L

ADDR_R

Address

Decoder

16R

R/W

BUSY

SEM

INT

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

R/W

BUSY

M/S

SEM

INT

TDI

TDO

JTAG

TMS

TCK

TRST

5621 drw 01

NOTES:

BUSY

is an input as a Slave (M/S=V

) and an output when it is a Master (M/S=V

BUSY

and

INT

are non-tri-state totem-pole outputs (push-pull).

JUNE 2001

DSC-5621/3

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