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IDT70V639S12BCI

Description
128K X 18 DUAL-PORT SRAM, 12 ns, PBGA208
Categorystorage   
File Size189KB,23 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Download Datasheet Parametric View All

IDT70V639S12BCI Overview

128K X 18 DUAL-PORT SRAM, 12 ns, PBGA208

IDT70V639S12BCI Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals208
Maximum operating temperature85 Cel
Minimum operating temperature-40 Cel
Maximum supply/operating voltage3.45 V
Minimum supply/operating voltage3.15 V
Rated supply voltage3.3 V
maximum access time12 ns
Processing package description15 × 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, FPBGA-208
stateACTIVE
CraftsmanshipCMOS
packaging shapeSQUARE
Package SizeGRID ARRAY, THIN PROFILE, FINE PITCH
surface mountYes
Terminal formBALL
Terminal spacing0.8000 mm
terminal coatingtin lead
Terminal locationBOTTOM
Packaging MaterialsPlastic/Epoxy
Temperature levelINDUSTRIAL
memory width18
organize128K × 18
storage density2.36E6 deg
operating modeASYNCHRONOUS
Number of digits131072 words
Number of digits128K
Memory IC typedual-port static random access memory
serial parallelparallel
HIGH-SPEED 3.3V 128K x 18
ASYNCHRONOUS DUAL-PORT
STATIC RAM
x
PRELIMINARY
IDT70V639S
Features
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 10/12/15ns (max.)
– Industrial: 12/15ns (max.)
Dual chip enables allow for depth expansion without
external logic
IDT70V639 easily expands data bus width to 36 bits or
more using the Master/Slave select when cascading more
than one device
M/S = V
IH
for
BUSY
output flag on Master,
M/S = V
IL
for
BUSY
input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
UB
L
LB
L
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Fully asynchronous operation from either port
Separate byte controls for multiplexed bus and bus
matching compatibility
Supports JTAG features compliant to IEEE 1149.1
– Due to limited pin count, JTAG is not supported on the
128-pin TQFP package.
LVTTL-compatible, single 3.3V (±150mV) power supply for
core
LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)
power supply for I/Os and control signals on each port
Available in a 128-pin Thin Quad Flatpack, 208-ball fine
pitch Ball Grid Array, and 256-ball Ball Grid Array
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Functional Block Diagram
UB
R
LB
R
R/W
L
B
E
0
L
B
E
1
L
B
E
1
R
B
E
0
R
R/W
R
CE
0L
CE
1L
CE
0R
CE
1R
OE
L
Dout0-8_L
Dout9-17_L
Dout0-8_R
Dout9-17_R
OE
R
128K x 18
MEMORY
ARRAY
I/O
0L
- I/O
17L
Din_L
Din_R
I/O
0R
- I/O
17R
A
16L
A
0L
Address
Decoder
ADDR_L
ADDR_R
Address
Decoder
A
16R
A
0R
OE
L
CE
0L
CE
1L
R/W
L
BUSY
L
SEM
L
INT
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
OE
R
CE
0R
CE
1R
R/W
R
BUSY
R
M/S
SEM
R
INT
R
TDI
TDO
JTAG
TMS
TCK
TRST
5621 drw 01
NOTES:
1.
BUSY
is an input as a Slave (M/S=V
IL
) and an output when it is a Master (M/S=V
IH
).
2.
BUSY
and
INT
are non-tri-state totem-pole outputs (push-pull).
JUNE 2001
DSC-5621/3
1
©2001 Integrated Device Technology, Inc.
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