1892Y-14LFT datasheet, PDF - EEWORLD Datasheet

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1892Y-14LFT: DescriptionSerial I/O Controller, 1 Channel(s), 12.5MBps, CMOS, PQFP64, 14 X 14 MM, ROHS COMPLIANT, LQFP-64; CategoryThe embedded processor and controller Microcontrollers and processors; File Size667KB，148 Pages; ManufacturerIDT (Integrated Device Technology)

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1892Y-14LFT Overview

Serial I/O Controller, 1 Channel(s), 12.5MBps, CMOS, PQFP64, 14 X 14 MM, ROHS COMPLIANT, LQFP-64

1892Y-14LFT Parametric

Parameter Name	Attribute value
Parts packaging code	QFP
package instruction	LQFP,
Contacts	64
Reach Compliance Code	unknown
ECCN code	EAR99
Is Samacsys	N
Address bus width
boundary scan	NO
maximum clock frequency	25 MHz
letter of agreement	SYNC, BYTE
Data encoding/decoding methods	NRZ; NRZI; BIPH-LEVEL(MANCHESTER)
Maximum data transfer rate	12.5 MBps
External data bus width
JESD-30 code	S-PQFP-G64
length	14 mm
low power mode	YES
Number of serial I/Os	1
Number of terminals	64
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Package shape	SQUARE
Package form	FLATPACK
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	QUAD
width	14 mm
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL
Base Number Matches	1

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Integrated Circuit Systems, Inc.

ICS1892

10Base-T/100Base-TX Integrated PHYceiver

General

The ICS1892, an enhanced version of the ICS 1890, is a

fully integrated, physical-layer device (PHY) that is

compliant with both the 10Base-T and 100Base-TX

CSMA/CD Ethernet Standard, ISO/IEC 8802-3.

The ICS1892 incorporates digital signal processing (DSP)

in its Physical Medium Dependent (PMD) sublayer. As a

result, it can transmit and receive data on unshielded

twisted-pair (UTP) category 5 cable with attenuation in

excess of 24 dB at 100 MHz. With this ICS-patented

technology, the ICS1892 can virtually eliminate errors from

killer packets.

The ICS1892 supports a broad range of applications: data

terminal equipm ent (netwo rk in terf ace card s and

motherboards), switches, repeaters, bridges, and routers. Its

Media Independent Interface (MII) supports direct

c h i p - t o - c h i p a n d m o t h e r b o a r d - t o - d a u g h t e r b o ar d

connections as well as connections to an MII connector and

cable. The ICS1892 also provides a Serial Management

Interface for exchanging command and status information

with a Station Management (STA) entity.

The ICS1892 Media Dependent Interface (MDI) can be

configured to provide either half- or full-duplex operation at

data rates of 10 MHz or 100 MHz. The MDI configuration

can be done manually (with input pins or control register

settings) or automatically (using the Auto-Negotiation

features). When the ICS1892 Auto-Negotiation sublayer is

enabled, it exchanges technology capability data with its

remote link partner and automatically selects the

highest-performance operating mode they have in common.

ICS1892 Block Diagram

100Base-T

10/100 MII or

Alternate

MAC/Repeater

Interface

MUX

PCS

• Frame

• CRS/COL

Detection

• Parallel to Serial

• 4B/5B

PMA

• Clock Recovery

• Link Monitor

• Signal Detection

• Error Detection

Document Type:

Data Sheet

Document Stage: Released

Features

•

Supports category 5 cables with attenuation in excess of

•

24 dB at 100 MHz across a temperature range from -5° to

+85° C

DSP-based baseline wander correction to virtually

eliminate killer packets across temperature range of from

-5° to +85° C

Low-power, 0.5-micron CMOS

Single 5.0-V power supply.

Single-chip, fully integrated PHY provides PCS, PMA,

PMD, and AUTONEG sublayers of IEEE standard

10Base-T and 100Base-TX IEEE 802.3 compliant

Fully integrated, DSP-based PMD includes:

– Adaptive equalization and baseline wander correction

– Transmit wave shaping and stream cipher scrambler

– MLT-3 encoder and NRZ/NRZI encoder

–

Node, repeater, and switch applications

Managed and unmanaged applications

10M or 100M half- and full-duplex modes

Parallel detection

Auto-negotiation, with Next Page capabilities

•

Highly configurable design supports:

•

MAC/Repeater Interface can be configured as:

– 10M or 100M Media Independent Interface

– 100M Symbol Interface (bypasses the PCS)

– 10M 7-wire Serial Interface

•

Provides Loopback Modes for Diagnostic Functions

•

Small Footprint 64-pin Low-Profile LQFP and MQFP

packages available

TP_PMD

• MLT-3

• Stream Cipher

• Adaptive Equalizer

• Baseline Wander

Correction

Integrated

Switch

10Base-T

MII

Extended

Set

Low-Jitter

Clock

Synthesizer

Clock

Power

Twisted-

Pair

Interface to

Magnetics

Modules and

RJ45

Connector

MII Serial

Management

Interface

Configuration

and Status

Auto-

Negotiation

LEDs and PHY

Address

1892 Rev. D, 2/26/01

ICS reserves the right to make changes in the device data identified in

this publication without further notice. ICS advises its customers to

obtain the latest version of all device data to verify that any information

being relied upon by the customer is current and accurate.

ICS1892 Data Sheet

Table of Contents

Section

Chapter 1

Chapter 2

Chapter 3

Chapter 4

4.1

4.2

Title

Page

Abbreviations and Acronyms................................................................9

Conventions and Nomenclature..........................................................11

ICS 1892 Enhanced Features.............................................................. 13

Overview of the ICS 1892 .................................................................... 15

100Base-TX Operation .............................................................................. 16

10Base-T Operation .................................................................................. 16

Chapter 5

5.1

5.1.1

5.1.2

5.2

5.3

5.4

5.5

5.6

5.7

Operating Modes Overview ................................................................ 17

Reset Operations ....................................................................................... 18

General Reset Operations ......................................................................... 18

Specific Reset Operations ......................................................................... 19

Power-Down Operations ........................................................................... 20

Automatic Power-Saving Operations ......................................................... 21

Auto-Negotiation Operations ..................................................................... 21

100Base-TX Operations ............................................................................ 22

10Base-T Operations ................................................................................ 22

Half-Duplex and Full-Duplex Operations ................................................... 22

Chapter 6

6.1

6.2

6.3

6.4

6.5

6.6

6.7

6.7.1

6.7.2

6.8

6.9

Interface Overviews ............................................................................. 23

MII Data Interface ...................................................................................... 24

100M Symbol Interface .............................................................................. 25

10M Serial Interface .................................................................................. 27

Link Pulse Interface ................................................................................... 29

Serial Management Interface .................................................................... 30

Twisted-Pair Interface ................................................................................ 30

Clock Reference Interface ......................................................................... 30

Clock Source: Oscillator or CMOS Driver .................................................. 30

Clock Source: Crystal ................................................................................ 31

Configuration Interface .............................................................................. 32

Status Interface ......................................................................................... 32

Chapter 7

7.1

7.2

7.2.1

7.2.2

7.2.3

7.2.4

7.2.5

Functional Blocks ................................................................................ 33

Functional Block: Media Independent Interface ........................................ 34

Functional Block: Auto-Negotiation ........................................................... 35

Auto-Negotiation General Process ............................................................ 36

Auto-Negotiation: Parallel Detection .......................................................... 37

Auto-Negotiation: Remote Fault Signaling ................................................ 37

Auto-Negotiation: Reset and Restart ......................................................... 38

Auto-Negotiation: Progress Monitor .......................................................... 39

ICS1892, Rev. D, 2/26/01

February 26, 2001

ICS1892

Table of Contents

Section

7.3

7.3.1

7.3.2

7.3.3

7.3.4

7.3.5

7.3.6

7.4

7.4.1

7.4.2

7.4.3

7.4.4

7.4.5

7.4.6

7.4.7

7.4.8

7.5

7.5.1

7.5.2

7.5.3

7.5.4

7.5.5

7.5.6

7.5.7

7.5.8

7.5.9

7.5.10

7.5.11

7.5.12

7.5.13

7.5.14

7.6

7.6.1

7.6.2

Title

Page

Functional Block: 100Base-X PCS and PMA Sublayers ........................... 41

PCS Sublayer ............................................................................................ 41

PMA Sublayer ............................................................................................ 41

PCS/PMA Transmit Modules ..................................................................... 42

PCS/PMA Receive Modules ...................................................................... 43

PCS Control Signal Generation ................................................................. 44

4B/5B Encoding/Decoding ......................................................................... 45

Functional Block: 100Base-TX TP-PMD Operations ................................. 46

100Base-TX Operation: Stream Cipher Scrambler/Descrambler .............. 46

100Base-TX Operation: MLT-3 Encoder/Decoder .................................... 46

100Base-TX Operation: DC Restoration ................................................... 46

100Base-TX Operation: Adaptive Equalizer .............................................. 47

100Base-TX Operation: Twisted-Pair Transmitter ..................................... 47

100Base-TX Operation: Twisted-Pair Receiver ......................................... 47

100Base-TX Operation: Auto Polarity Correction ...................................... 48

100Base-TX Operation: Isolation Transformer .......................................... 48

Functional Block: 10Base-T Operations .................................................... 49

10Base-T Operation: Manchester Encoder/Decoder ................................ 49

10Base-T Operation: Clock Synthesis ....................................................... 49

10Base-T Operation: Clock Recovery ....................................................... 49

10Base-T Operation: Idle .......................................................................... 50

10Base-T Operation: Link Monitor ............................................................. 50

10Base-T Operation: Smart Squelch ......................................................... 51

10Base-T Operation: Carrier Detection ..................................................... 51

10Base-T Operation: Collision Detection .................................................. 51

10Base-T Operation: Jabber ..................................................................... 52

10Base-T Operation: SQE Test ................................................................. 52

10Base-T Operation: Twisted-Pair Transmitter ......................................... 53

10Base-T Operation: Twisted-Pair Receiver ............................................. 53

10Base-T Operation: Auto Polarity Correction .......................................... 54

10Base-T Operation: Isolation Transformer .............................................. 54

Functional Block: Management Interface .................................................. 55

Management Register Set Summary ........................................................ 55

Management Frame Structure ................................................................... 55

ICS1892, Rev. D, 2/26/01

February 26, 2001

ICS1892 Data Sheet

Table of Contents

Section

Chapter 8

8.1

8.1.1

8.1.2

8.1.3

8.1.4

8.2

8.2.1

8.2.2

8.2.3

8.2.4

8.2.5

8.2.6

8.2.7

8.2.8

8.2.9

8.2.10

8.3

8.3.1

8.3.2

8.3.3

8.3.4

8.3.5

8.3.6

8.3.7

8.3.8

8.3.9

8.3.10

8.3.11

8.3.12

8.3.13

8.4

Title

Page

Management Register Set................................................................... 58

Introduction to Management Register Set ................................................. 59

Management Register Set Outline ............................................................ 59

Management Register Bit Access ............................................................. 60

Management Register Bit Default Values .................................................. 60

Management Register Bit Special Functions ............................................. 61

Reset (bit 0.15) .......................................................................................... 62

Loopback Enable (bit 0.14) ........................................................................ 63

Data Rate Select (bit 0.13) ........................................................................ 63

Auto-Negotiation Enable (bit 0.12) ............................................................ 63

Low Power Mode (bit 0.11) ........................................................................ 64

Isolate (bit 0.10) ......................................................................................... 64

Restart Auto-Negotiation (bit 0.9) .............................................................. 64

Duplex Mode (bit 0.8) ................................................................................ 65

Collision Test (bit 0.7) ................................................................................ 65

IEEE Reserved Bits (bits 0.6:0) ................................................................. 65

100Base-T4 (bit 1.15) ................................................................................ 66

100Base-TX Full Duplex (bit 1.14) ............................................................ 67

100Base-TX Half Duplex (bit 1.13) ............................................................ 67

10Base-T Full Duplex (bit 1.12) ................................................................. 67

10Base-T Half Duplex (bit 1.11) ................................................................ 67

IEEE Reserved Bits (bits 1.10:7) ............................................................... 68

MF Preamble Suppression (bit 1.6) ........................................................... 68

Auto-Negotiation Complete (bit 1.5) .......................................................... 68

Remote Fault (bit 1.4) ................................................................................ 69

Auto-Negotiation Ability (bit 1.3) ................................................................ 69

Link Status (bit 1.2) .................................................................................... 69

Jabber Detect (bit 1.1) ............................................................................... 70

Extended Capability (bit 1.0) ..................................................................... 70

ICS1892, Rev. D, 2/26/01

February 26, 2001

ICS1892

Table of Contents

Section

8.5

8.5.1

8.5.2

8.5.3

8.6

8.6.1

8.6.2

8.6.3

8.6.4

8.6.5

8.7

8.7.1

8.7.2

8.7.3

8.7.4

8.7.5

8.8

8.8.1

8.8.2

8.8.3

8.8.4

8.8.5

8.8.6

8.9

8.9.1

8.9.2

8.9.3

8.9.4

8.9.5

8.9.6

8.10

8.10.1

8.10.2

8.10.3

8.10.4

8.10.5

Title

Page

OUI bits 19-24 (bits 3.15:10) ..................................................................... 73

Manufacturer's Model Number (bits 3.9:4) ................................................ 73

Revision Number (bits 3.3:0) ..................................................................... 74

Next Page (bit 4.15) ................................................................................... 75

IEEE Reserved Bit (bit 4.14) ...................................................................... 76

Remote Fault (bit 4.13) .............................................................................. 76

Technology Ability Field (bits 4.12:5) ......................................................... 76

Selector Field (Bits 4.4:0) .......................................................................... 77

Next Page (bit 5.15) ................................................................................... 78

Acknowledge (bit 5.14) .............................................................................. 79

Remote Fault (bit 5.13) .............................................................................. 79

Technology Ability Field (bits 5.12:5) ......................................................... 79

Selector Field (bits 5.4:0) ........................................................................... 79

IEEE Reserved Bits (bits 6.15:5) ............................................................... 80

Parallel Detection Fault (bit 6.4) ................................................................ 81

Link Partner Next Page Able (bit 6.3) ........................................................ 81

Next Page Able (bit 6.2) ............................................................................ 81

Page Received (bit 6.1) ............................................................................. 81

Link Partner Auto-Negotiation Able (bit 6.0) .............................................. 81

Next Page (bit 7.15) ................................................................................... 83

IEEE Reserved Bit (bit 7.14) ...................................................................... 83

Message Page (bit 7.13) ........................................................................... 83

Acknowledge 2 (bit 7.12) ........................................................................... 83

Toggle (bit 7.11) ........................................................................................ 83

Message Code Field / Unformatted Code Field (bits 7.10:0) .................... 83

Next Page (bit 8.15) ................................................................................... 85

IEEE Reserved Bit (bit 8.14) ...................................................................... 85

Message Page (bit 8.13) ........................................................................... 85

Acknowledge 2 (bit 8.12) ........................................................................... 85

Message Code Field / Unformatted Code Field (bits 8.10:0) .................... 85

ICS1892, Rev. D, 2/26/01

February 26, 2001

1892Y-14LFT Related Products

	1892Y-14LFT	1892Y-10LFT	1892YLFT
Description	Serial I/O Controller, 1 Channel(s), 12.5MBps, CMOS, PQFP64, 14 X 14 MM, ROHS COMPLIANT, LQFP-64	Serial I/O Controller, 1 Channel(s), 12.5MBps, CMOS, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64	Serial I/O Controller, 1 Channel(s), 12.5MBps, CMOS, PQFP64, 14 X 14 MM, ROHS COMPLIANT, MQFP-64
Parts packaging code	QFP	QFP	QFP
package instruction	LQFP,	LFQFP,	QFP,
Contacts	64	64	64
Reach Compliance Code	unknown	unknown	unknown
Is Samacsys	N	N	N
boundary scan	NO	NO	NO
maximum clock frequency	25 MHz	25 MHz	25 MHz
letter of agreement	SYNC, BYTE	SYNC, BYTE	SYNC, BYTE
Data encoding/decoding methods	NRZ; NRZI; BIPH-LEVEL(MANCHESTER)	NRZ; NRZI; BIPH-LEVEL(MANCHESTER)	NRZ; NRZI; BIPH-LEVEL(MANCHESTER)
Maximum data transfer rate	12.5 MBps	12.5 MBps	12.5 MBps
JESD-30 code	S-PQFP-G64	S-PQFP-G64	S-PQFP-G64
length	14 mm	10 mm	14 mm
low power mode	YES	YES	YES
Number of serial I/Os	1	1	1
Number of terminals	64	64	64
Maximum operating temperature	70 °C	70 °C	70 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LQFP	LFQFP	QFP
Package shape	SQUARE	SQUARE	SQUARE
Package form	FLATPACK	FLATPACK	FLATPACK
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.6 mm	1.6 mm	3 mm
Maximum supply voltage	5.25 V	5.25 V	5.25 V
Minimum supply voltage	4.75 V	4.75 V	4.75 V
Nominal supply voltage	5 V	5 V	5 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	GULL WING	GULL WING	GULL WING
Terminal pitch	0.8 mm	0.5 mm	0.8 mm
Terminal location	QUAD	QUAD	QUAD
width	14 mm	10 mm	14 mm
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL
Base Number Matches	1	1	1
ECCN code	EAR99	EAR99	-

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