27LV64
64K (8K x 8) Low-Voltage CMOS EPROM
FEATURES
• Wide voltage range 3.0V to 5.5V
• High speed performance
- 200 ns access time available at 3.0V
• CMOS Technology for low power consumption
- 8 mA active current at 3.0V
- 20 mA active current at 5.5V
- 100
µ
A standby current
• Factory programming available
• Auto-insertion-compatible plastic packages
• Auto ID aids automated programming
• Separate chip enable and output enable controls
• High speed “express” programming algorithm
• Organized 8K x 8: JEDEC standard pinouts
- 28-pin Dual-in-line package
- 32-pin PLCC Package
- 28-pin SOIC package
- Tape and reel
• Available for the following temperature ranges:
- Commercial:
0˚C to +70˚C
- Industrial:
-40˚C to +85˚C
PACKAGE TYPES
DIP/SOIC
V
PP
A12
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
V
SS
•1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
PGM
NC
A8
A9
A11
OE
A10
CE
O7
O6
O5
O4
O3
27LV64
PLCC
A7
A12
V
PP
NU
Vcc
PGM
NC
4
3
2
1
32
31
30
DESCRIPTION
The Microchip Technology Inc. 27LV64 is a low-voltage
(3.0 volt) CMOS EPROM designed for battery powered
applications. The device is organized as 8K x 8 (8K-
Byte) non-volatile memory product. The 27LV64 con-
sumes only 8mA maximum of active current during a
3.0 volt read operation therefore improving battery per-
formance. This device is designed for very low voltage
applications where conventional 5.0 volt only EPROMs
can not be used. Accessing individual bytes from an
address transition or from power-up (chip enable pin
going low) is accomplished in less than 200 ns at
3.0V.This device allows system designers the ability to
use low voltage non-volatile memory with today’s low
voltage microprocessors and peripherals in battery
powered applications.
A complete family of packages is offered to provide the
most flexibility in applications. For surface mount appli-
cations, PLCC or SOIC packaging is available. Tape
and reel packaging is also available for PLCC or SOIC
packages.
A6
A5
A4
A3
A2
A1
A0
NC
O0
5
6
29
28
7
8
9
10
11
12
13
14
15
16
27
26
25
24
23
22
21
A8
A9
A11
NC
OE
A10
CE
O7
O6
17
18
19
©
1996 Microchip Technology Inc.
O1
O2
V
SS
NU
O3
O4
O5
20
27LV64
DS11024E-page 1
This document was created with FrameMaker 4 0 4
27LV64
1.0
1.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
TABLE 1-1:
Name
A0-A12
CE
OE
PGM
V
PP
O0 - O7
V
CC
V
SS
NC
NU
PIN FUNCTION TABLE
Function
Address Inputs
Chip Enable
Output Enable
Program Enable
Programming Voltage
Data Output
+5V Or +3V Power Supply
Ground
No Connection; No Internal Connec-
tions
Not Used; No External Connection Is
Allowed
V
CC
and input voltages w.r.t. V
SS
....... -0.6V to + 7.25V
V
PP
voltage w.r.t. V
SS
during
programming .......................................... -0.6V to +14V
Voltage on A9 w.r.t. V
SS
...................... -0.6V to +13.5V
Output voltage w.r.t. V
SS
............... -0.6V to V
CC
+1.0V
Storage temperature .......................... -65˚C to +150˚C
Ambient temp. with power applied ..... -65˚C to +125˚C
*Notice: Stresses above those listed under “Maximum Ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operation listings of
this specification is not implied. Exposure to maximum rating con-
ditions for extended periods may affect device reliability.
TABLE 1-2:
READ OPERATION DC CHARACTERISTICS
V
CC
= 3.0V to 5.5V unless otherwise specified
Commercial:
Tamb = 0˚C to +70˚C
Industrial:
Tamb = -40˚C to +85˚C
Parameter
Input Voltages
Input Leakage
Output Voltages
Output Leakage
Input Capacitance
Output Capacitance
Power Supply Current,
Active
Part*
all
all
all
all
all
all
C
I
Status
Logic "1"
Logic "0"
—
Logic "1"
Logic "0"
—
—
—
TTL input
TTL input
Symbol
V
IH
V
IL
I
LI
V
OH
V
OL
I
LO
C
IN
C
OUT
I
CC1
I
CC2
Min.
2.0
-0.5
-10
2.4
Max.
V
CC
+1
0.8
10
0.45
Units
V
V
µ
A
V
V
µ
A
pF
pF
mA
mA
mA
mA
Conditions
V
IN
= 0 to V
CC
I
OH
= -400
µ
A
I
OL
= 2.1 mA
V
OUT
= 0V to V
CC
V
IN
= 0V; Tamb = 25
°
C;
f = 1 MHz
V
OUT
= 0V; Tamb = 25
°
C;
f = 1 MHz
V
CC
= 5.5V; V
PP
= V
CC
f = 1 MHz;
OE = CE = V
IL
;
I
OUT
= 0 mA;
V
IL
= -0.1 to 0.8V;
V
IH
= 2.0 to V
CC
;
Note 1
-10
—
—
—
—
10
6
12
20 @ 5.0V
8 @ 3.0V
25 @ 5.0V
10 @ 3.0V
Power Supply Current,
Standby
C
I
all
TTL input
TTL input
CMOS input
I
CC
(
S
)
—
1 @ 3.0V
2@ 3.0V
100 @ 3.0V
mA
mA
µ
A
CE = V
CC
±
0.2V
* Parts: C=Commercial Temperature Range; I=Industrial Temperature Range
Note 1: Typical active current increases .5 mA per MHz up to operating frequency for all temperature ranges.
DS11024E-page 2
©
1996 Microchip Technology Inc.
27LV64
TABLE 1-3:
READ OPERATION AC CHARACTERISTICS
AC Testing Waveform:
Output Load:
Input Rise and Fall Times:
Ambient Temperature:
27LV64-20
Parameter
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE to O/P High
Impedance
Output Hold from Address CE or
OE, whichever goes first
Sym
Min.
t
ACC
t
CE
t
OE
t
OFF
t
OH
—
—
—
0
0
Max.
200
200
100
50
—
Min.
—
—
—
0
0
Max.
250
250
125
50
—
Min.
—
—
—
0
0
Max.
300
300
125
50
—
ns
ns
ns
ns
ns
CE = OE = V
IL
OE = V
IL
CE = V
IL
V
IH
= 2.4V and V
IL
= 0.45V; V
OH
= 2.0V V
OL
= 0.8V
1 TTL Load + 100 pF
10 ns
Commercial:
Tamb = 0˚C to +70˚C
Industrial:
Tamb = -40˚C to +85˚C
27LV64-30
Units
Conditions
27LV64-25
FIGURE 1-1:
V
IH
Address
V
IL
V
IH
CE
V
IL
READ WAVEFORMS
Address Valid
t
CE(2)
V
IH
OE
V
IL
V
OH
V
OL
t
ACC
t
OE(2)
High Z
t
OFF(1,3)
t
OH
Valid Output
High Z
Outputs
O0 - O7
Notes: (1) t
OFF
is specified for OE or CE, whichever occurs first
(2) OE may be delayed up to t
CE
- t
OE
after the falling edge of CE without impact on t
CE
(3) This parameter is sampled and is not 100% tested.
©
1996 Microchip Technology Inc.
DS11024E-page 3
27LV64
TABLE 1-4:
PROGRAMMING DC CHARACTERISTICS
Ambient Temperature: Tamb = 25
°
C
±
5
°
C
V
CC
= 6.5V
±
0.25V, V
PP
= V
H
= 13.0V
±
0.25V
Parameter
Input Voltages
Input Leakage
Output Voltages
V
CC
Current, program & verify
V
PP
Current, program
A9 Product Identification
Status
Logic”1”
Logic”0”
—
Logic”1”
Logic”0”
—
—
—
Symbol
V
IH
V
IL
I
LI
V
OH
V
OL
I
CC2
I
PP2
V
H
Min.
2.0
-0.1
-10
2.4
0.45
—
—
11.5
20
25
12.5
Max.
V
CC
+1
0.8
10
Units
V
V
µ
A
V
V
mA
mA
V
V
IN
= 0V to V
CC
I
OH
= -400
µ
A
I
OL
= 2.1 mA
Note 1
Note 1
Conditions
Note 1: V
CC
must be applied simultaneously or before V
PP
and removed simultaneously or after V
PP
.
TABLE 1-5:
PROGRAMMING AC CHARACTERISTICS
AC Testing Waveform: V
IH
=2.4V and V
IL
=0.45V; V
OH
=2.0V; V
OL
=0.8V
Ambient Temperature: Tamb=25
°
C
±
5
°
C
V
CC
= 6.5V
±
0.25V, V
PP
= V
H
= 13.0V
±
0.25V
Symbol
t
AS
t
DS
t
DH
t
AH
t
DF
t
VCS
t
PW
t
CES
t
OES
t
VPS
t
OE
Min.
2
2
2
0
0
2
95
2
2
2
Max.
—
—
—
—
130
—
105
—
—
—
100
Units
µs
µs
µs
µs
ns
µs
µs
µs
µs
µs
ns
100
µs
typical
Remarks
for Program, Program Verify
and Program Inhibit Modes
Parameter
Address Set-Up Time
Data Set-Up Time
Data Hold Time
Address Hold Time
Float Delay (2)
V
CC
Set-Up Time
Program Pulse Width (1)
CE Set-Up Time
OE Set-Up Time
V
PP
Set-Up Time
Data Valid from OE
Note 1: For express algorithm, initial programming width tolerance is 100
µs ±5%.
Note 2: This parameter is only sampled and not 100% tested. Output float is defined as the point where data is no
longer driven (see timing diagram).
DS11024E-page 4
©
1996 Microchip Technology Inc.
27LV64
FIGURE 1-2:
PROGRAMMING WAVEFORMS (1)
Program
V
IH
Address
V
IL
t
AS
V
IH
Data
V
IL
t
DS
13.0 V (3)
V
PP
5.0 V
6.5 V (3)
V
CC
5.0 V
V
IH
CE
V
IL
t
CES
V
IH
PGM
V
IL
t
PW
V
IH
OE
V
IL
Notes: (1) The input timing reference is 0.8V for V
IL
and 2.0V for V
IH
.
(2) t
DF
and t
OE
are characteristics of the device but must be accommodated by the programmer.
(3) Vcc = 6.5V
±0.25V,
V
PP
= V
H
= 13.0V
±0.25V
for Express algorithm.
t
OPW
t
OES
t
OE
(2)
t
VCS
t
VPS
Data In Stable
t
DH
High Z
Data Out Valid
t
DF
(2)
t
AH
Address Stable
Verify
TABLE 1-6:
MODES
CE
V
IL
V
IL
V
IL
V
IH
V
IH
V
IL
V
IL
OE
V
IL
V
IH
V
IL
X
X
V
IH
V
IL
PGM
V
IH
V
IL
V
IH
X
X
V
IH
V
IH
V
PP
V
CC
V
H
V
H
V
H
V
CC
V
CC
V
CC
A9
X
X
X
X
X
X
V
H
O0 - O7
D
OUT
D
IN
D
OUT
High Z
High Z
High Z
Identity Code
Operation Mode
Read
Program
Program Verify
Program Inhibit
Standby
Output Disable
Identity
X = Don’t Care
1.2
Read Mode
(See Timing Diagrams and AC Characteristics)
Read Mode is accessed when
a)
b)
the CE pin is low to power up (enable) the chip
the OE pin is low to gate the data to the output
pins
For Read operations, if the addresses are stable, the
address access time (t
ACC
) is equal to the delay from
CE to output (t
CE
). Data is transferred to the output
after a delay from the falling edge of OE (t
OE
).
©
1996 Microchip Technology Inc.
DS11024E-page 5
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