DATA SHEET
MOS FIELD EFFECT TRANSISTOR
NP80N055ELE, NP80N055KLE
NP80N055CLE, NP80N055DLE, NP80N055MLE, NP80N055NLE
SWITCHING
N-CHANNEL POWER MOS FET
DESCRIPTION
These products are N-channel MOS Field Effect Transistors designed for high current switching applications.
<R>
ORDERING INFORMATION
PART NUMBER
NP80N055ELE-E1-AY
NP80N055ELE-E2-AY
NP80N055KLE-E1-AY
NP80N055KLE-E2-AY
Note1, 2
Note1, 2
Note1
Note1
Note1, 2
Note1, 2
Note1
Note1
LEAD PLATING
PACKING
PACKAGE
TO-263 (MP-25ZJ) typ. 1.4 g
Pure Sn (Tin)
Tape 800 p/reel
TO-263 (MP-25ZK) typ. 1.5 g
NP80N055CLE-S12-AZ
NP80N055DLE-S12-AY
NP80N055MLE-S18-AY
NP80N055NLE-S18-AY
Sn-Ag-Cu
Tube 50 p/tube
TO-220 (MP-25) typ. 1.9 g
TO-262 (MP-25 Fin Cut) typ. 1.8 g
TO-220 (MP-25K) typ. 1.9 g
TO-262 (MP-25SK) typ. 1.8 g
Pure Sn (Tin)
Notes 1.
Pb-free (This product does not contain Pb in the external electrode.)
2.
Not for new design
(TO-220)
FEATURES
•
Channel temperature 175 degree rated
•
Super low on-state resistance
R
DS(on)1
= 11 mΩ MAX. (V
GS
= 10 V, I
D
= 40 A)
R
DS(on)2
= 13 mΩ MAX. (V
GS
= 5 V, I
D
= 40 A)
R
DS(on)3
= 15 mΩ MAX. (V
GS
= 4.5 V, I
D
= 40 A)
•
Low input capacitance
C
iss
= 2900 pF TYP.
•
Built-in gate protection diode
(TO-262)
(TO-263)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. D14097EJ6V0DS00 (6th edition)
Date Published October 2007 NS
Printed in Japan
2002, 2007
The mark <R> shows major revised points.
The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.
NP80N055ELE, NP80N055KLE, NP80N055CLE, NP80N055DLE, NP80N055MLE, NP80N055NLE
ABSOLUTE MAXIMUM RATINGS (T
A
= 25°C)
Drain to Source Voltage (V
GS
= 0 V)
Gate to Source Voltage (V
DS
= 0 V)
Drain Current (DC) (T
C
= 25°C)
Drain Current (Pulse)
Note2
Note1
V
DSS
V
GSS
I
D(DC)
I
D(pulse)
P
T
P
T
T
ch
T
stg
55
±20
±80
±200
120
1.8
175
−55
to
+175
45/30/10
2.0/90/100
V
V
A
A
W
W
°C
°C
A
mJ
Total Power Dissipation (T
C
= 25°C)
Total Power Dissipation (T
A
= 25°C)
Channel Temperature
Storage Temperature
Single Avalanche Current
Single Avalanche Energy
Note3
Note3
I
AS
E
AS
Notes 1.
Calculated constant current according to MAX. allowable channel temperature.
2.
PW
≤
10
μ
s, Duty cycle
≤
1%
3.
Starting T
ch
= 25°C, V
DD
= 28 V, R
G
= 25
Ω,
V
GS
= 20→0 V (see
Figure 4.)
THERMAL RESISTANCE
Channel to Case Thermal Resistance
Channel to Ambient Thermal Resistance
R
th(ch-C)
R
th(ch-A)
1.25
83.3
°C/W
°C/W
2
Data Sheet D14097EJ6V0DS
NP80N055ELE, NP80N055KLE, NP80N055CLE, NP80N055DLE, NP80N055MLE, NP80N055NLE
ELECTRICAL CHARACTERISTICS (T
A
= 25°C)
CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate Leakage Current
Gate to Source Threshold Voltage
Forward Transfer Admittance
Drain to Source On-state Resistance
SYMBOL
I
DSS
I
GSS
V
GS(th)
| y
fs
|
R
DS(on)1
R
DS(on)2
R
DS(on)3
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Total Gate Charge
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
G1
Q
G2
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Q
GS
Q
GD
V
F(S-D)
t
rr
Q
rr
V
DD
= 44 V, V
GS
= 10 V, I
D
= 80 A
V
DD
= 44 V,
V
GS
= 5 V,
I
D
= 80 A
I
F
= 80 A, V
GS
= 0 V
I
F
= 80 A, V
GS
= 0 V,
di/dt = 100 A/
μ
s
TEST CONDITIONS
V
DS
= 55 V, V
GS
= 0 V
V
GS
=
±20
V, V
DS
= 0 V
V
DS
= V
GS
, I
D
= 250
μ
A
V
DS
= 10 V, I
D
= 40 A
V
GS
= 10 V, I
D
= 40 A
V
GS
= 5 V, I
D
= 40 A
V
GS
= 4.5 V, I
D
= 40 A
V
DS
= 25 V,
V
GS
= 0 V,
f = 1 MHz
V
DD
= 28 V, I
D
= 40 A,
V
GS
= 10 V,
R
G
= 1
Ω
1.5
15
2.0
40
8.4
10.3
11.3
2900
380
170
22
10
62
11
50
26
12
15
1.0
50
100
11
13
15
4400
570
310
48
25
120
27
75
39
MIN.
TYP.
MAX.
10
±10
2.5
UNIT
μ
A
μ
A
V
S
mΩ
mΩ
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
nC
V
ns
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
R
G
= 25
Ω
PG.
V
GS
= 20
→
0 V
50
Ω
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
L
V
DD
PG.
R
G
V
GS
R
L
V
DD
V
DS
90%
90%
10%
10%
V
GS
Wave Form
0
10%
V
GS
90%
BV
DSS
I
AS
I
D
V
DD
V
DS
V
GS
0
τ
τ
= 1
μs
Duty Cycle
≤
1%
V
DS
V
DS
Wave Form
0
t
d(on)
t
on
t
r
t
d(off)
t
off
t
f
Starting T
ch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
I
G
= 2 mA
PG.
50
Ω
R
L
V
DD
Data Sheet D14097EJ6V0DS
3
NP80N055ELE, NP80N055KLE, NP80N055CLE, NP80N055DLE, NP80N055MLE, NP80N055NLE
TYPICAL CHARACTERISTICS (T
A
= 25°C)
Figure1. DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
Figure2. TOTAL POWER DISSIPATION vs.
CASE TEMPERATURE
140
P
T
- Total Power Dissipation - W
dT - Percentage of Rated Power - %
100
80
60
40
20
0
120
100
80
60
40
20
0
0
25
50
75
100 125 150 175 200
0
25
50
75
100 125 150 175 200
T
C
- Case Temperature -
°C
T
C
- Case Temperature -
°C
Figure4. SINGLE AVALANCHE ENERGY
DERATING FACTOR
120
E
AS
- Single Avalanche Energy - mJ
Figure3. FORWARD BIAS SAFE OPERATING AREA
1000
I
D(pulse)
PW
10
0
μ
s
I
D
- Drain Current - A
100
d
ite
im )
)
L 0V
n
1
S(o
R
D
V
GS
=
(
=1
D(DC)
Po
DC
Lim wer
ite Dis
sip
d
ati
I
0
μ
s
100
80
60
40
20
100 mJ
90 mJ
I
AS
= 10 A
30 A
45 A
1m
s
on
10
1
T
C
= 25°C
Single Pulse
0.1
0.1
1
10
V
DS
- Drain to Source Voltage - V
100
2.0 mJ
0
25
50
75
100
125
150
175
Starting T
ch
- Starting Channel Temperature -
°C
Figure5. TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
1000
r
th(t)
- Transient Thermal Resistance -
°C/W
100
R
th(ch-A)
= 83.3°C/W
10
1
R
th(ch-C)
= 1.25°C/W
0.1
Single Pulse
0.01
10
μ
100
μ
1m
10 m
100 m
1
10
100
1000
PW - Pulse Width - s
4
Data Sheet D14097EJ6V0DS
NP80N055ELE, NP80N055KLE, NP80N055CLE, NP80N055DLE, NP80N055MLE, NP80N055NLE
Figure6. FORWARD TRANSFER CHARACTERISTICS
100 Pulsed
Figure7. DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
200
Pulsed
160
120
4.5 V
80
40
V
GS
=10 V
5V
I
D
- Drain Current - A
1
T
A
=
−50°C
25°C
75°C
150°C
175°C
0.1
0.01
I
D
- Drain Current - A
6
10
1
2
3
4
5
0
0
1
2
3
4
5
V
GS
- Gate to Source Voltage - V
V
DS
- Drain to Source Voltage - V
R
DS(on)
- Drain to Source On-state Resistance - mΩ
| y
fs
| - Forward Transfer Admittance - S
Figure8. FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
100
V
DS
= 10V
Pulsed
10
T
A
= 175°C
75°C
25°C
−50°C
Figure9. DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
50
Pulsed
40
30
20
10
0
I
D
= 40 A
1
0.1
0.01
0.01
0.1
1
10
100
0
2
4
6
8
10
12
14
16
18
I
D
- Drain Current - A
V
GS
- Gate to Source Voltage - V
R
DS(on)
- Drain to Source On-state Resistance - mΩ
30
Pulsed
V
GS(th)
- Gate to Source Threshold Voltage - V
Figure10. DRAIN TO SOURCE ON-STATE
RESISTANCE vs. DRAIN CURRENT
Figure11. GATE TO SOURCE THRESHOLD VOLTAGE vs.
CHANNEL TEMPERATURE
3.0
V
DS
= V
GS
I
D
= 250
μA
2.5
2.0
1.5
1.0
0.5
0
−50
20
V
GS
= 4.5 V
5V
10 V
10
0
1
10
100
1000
0
50
100
150
I
D
- Drain Current - A
T
ch
- Channel Temperature -
°C
Data Sheet D14097EJ6V0DS
5
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