1893BFT datasheet, PDF - EEWORLD Datasheet

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1893BFT: DescriptionInterface Circuit, 1-Trnsvr, CMOS, PDSO48, 0.300 INCH, SSOP-48; CategoryWireless rf/communication Telecom circuit; File Size812KB，138 Pages; ManufacturerIDT (Integrated Device Technology)

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1893BFT Overview

Interface Circuit, 1-Trnsvr, CMOS, PDSO48, 0.300 INCH, SSOP-48

1893BFT Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	SSOP
package instruction	0.300 INCH, SSOP-48
Contacts	48
Reach Compliance Code	not_compliant
data rate	100000 Mbps
JESD-30 code	R-PDSO-G48
JESD-609 code	e0
length	15.875 mm
Humidity sensitivity level	1
Number of functions	1
Number of terminals	48
Transceiver quantity	1
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	SSOP
Encapsulate equivalent code	SSOP48,.4
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	225
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	2.8 mm
Maximum slew rate	0.16 mA
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Telecom integrated circuit types	INTERFACE CIRCUIT
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.635 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	20
width	7.5 mm
Base Number Matches	1

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Integrated Device Technology, Inc.

ICS1893BF

General

The ICS1893BF is a low-power, physical-layer device (PHY)

that supports the ISO/IEC 10Base-T and 100Base-TX

Carrier-Sense Multiple Access/Collision Detection

(CSMA/CD) Ethernet standards, ISO/IEC 8802-3.

The ICS1893BF is intended for MII, Node applications that

require the Auto-MDIX feature that automatically corrects

crossover errors in plant wiring.

The ICS1893BF incorporates Digital-Signal Processing (DSP)

control in its Physical-Medium Dependent (PMD) sub layer. As

a result, it can transmit and receive data on unshielded

twisted-pair (UTP) category 5 cables with attenuation in

excess of 24 dB at 100MHz. With this ICS-patented

technology, the ICS1893BF can virtually eliminate errors from

killer packets.

The ICS1893BF provides a Serial-Management Interface for

exchanging command and status information with a

Sta t i o n - M a n a g e m e n t ( S TA ) e n t i t y. T h e I C S 1 8 9 3 B F

Media-Dependent Interface (MDI) can be configured to

provide either half- or full-duplex operation at data rates of 10

Mb/s or 100Mb/s.

The ICS1893BF is available in a 300-mil 48-lead SSOP

pac k a g e . T h e I CS 1 89 3 B F s h a r e s t h e s a m e p r o v en

performance circuitry with the ICS1893AF but is not a

pin-for-pin replacement of the 1893AF. An application note for

a dual footprint layout to accommodate ICS1893AF or

ICS1893BF is available on the ICS website.

Document Type:

Data Sheet

Document Stage: Rev. E Release

3.3-V 10Base-T/100Base-TX Integrated PHYceiver™

Features

•

Supports category 5 cables with attenuation in excess of

24dB at 100 MHz.

•

Single-chip, fully integrated PHY provides PCS, PMA, PMD,

and AUTONEG sub layers functions of IEEE standard.

10Base-T and 100Base-TX IEEE 8802.3 compliant

Single 3.3V power supply

Highly configurable, supports:

– Media Independent Interface (MII)

– Auto-Negotiation with Parallel detection

– Node applications, managed or unmanaged

– 10M or 100M full and half-duplex modes

– Loopback mode for Diagnostic Functions

– Auto-MDI/MDIX crossover correction

Low-power CMOS (typically 400 mW)

Power-Down mode typically 21mW

Clock and crystal supported

Fully integrated, DSP-based PMD includes:

– Adaptive equalization and baseline-wander correction

– Transmit wave shaping and stream cipher scrambler

– MLT-3 encoder and NRZ/NRZI encoder

Small footprint 48-pin 300 mil. SSOP package

Also available in small footprint 56-pin 8x8 MLF2 package

Available in Industrial Temp and Lead Free

•

Applications:

NIC cards, PC motherboards, switches,

routers, DSL and cable modems, game machines,

printers.

ICS1893BF Block Diagram

NOTE: EOL for non-green parts to occur on

5/13/10 per PDN U-09-01

100Base-T

10/100 MII

MAC

Interface

MUX

PCS

• Framer

• CRS/COL

Detection

• Parallel to Serial

• 4B/5B

PMA

• Clock Recovery

• Link Monitor

• Signal Detection

• Error Detection

TP_PMD

• MLT-3

• Stream Cipher

• Adaptive Equalizer

• Baseline Wander

Correction

Integrated

Switch

10Base-T

MII

Extended

Set

Low-Jitter

Clock

Synthesizer

Clock

Power

Twisted-

Pair

Interface to

Magnetics

Modules and

RJ45

Connector

MII

Management

Interface

Configuration

and Status

Auto-

Negotiation

LEDs and PHY

Address

ICS1893BF, Rev. E, 8/11/09

IDT reserves the right to make changes in the device data identified in

this publication without further notice. IDT advises its customers to

obtain the latest version of all device data to verify that any information

being relied upon by the customer is current and accurate.

August, 2009

ICS1893BF Data Sheet - Release

Table of Contents

Section

Chapter 1

Chapter 2

Chapter 3

3.1

3.2

Chapter 4

4.1

4.1.1

4.1.2

4.2

4.3

4.4

4.5

4.6

4.7

4.8

Chapter 5

5.1

5.2

5.3

5.3.1

5.4

5.5

Chapter 6

6.1

6.2

6.2.1

6.2.2

6.2.3

6.2.4

6.2.5

Title

Page

Abbreviations and Acronyms ......................................................................................... 10

Conventions and Nomenclature..................................................................................... 12

Overview of the ICS1893BF............................................................................................. 14

100Base-TX Operation .......................................................................................... 15

10Base-T Operation ............................................................................................... 15

Operating Modes Overview............................................................................................. 16

Reset Operations ................................................................................................... 17

General Reset Operations ..................................................................................... 17

Specific Reset Operations ..................................................................................... 18

Power-Down Operations ........................................................................................ 19

Automatic Power-Saving Operations ..................................................................... 20

Auto-Negotiation Operations .................................................................................. 20

100Base-TX Operations ........................................................................................ 21

10Base-T Operations ............................................................................................. 21

Half-Duplex and Full-Duplex Operations ............................................................... 21

Auto-MDI/MDIX Crossover ..................................................................................... 22

Interface Overviews.......................................................................................................... 23

MII Data Interface .................................................................................................. 24

Serial Management Interface ................................................................................. 25

Twisted-Pair Interface ............................................................................................ 25

Twisted-Pair Transmitter......................................................................................... 25

Clock Reference Interface ..................................................................................... 27

Status Interface ...................................................................................................... 29

Functional Blocks............................................................................................................. 31

Functional Block: Media Independent Interface ..................................................... 32

Functional Block: Auto-Negotiation ........................................................................ 33

Auto-Negotiation General Process ........................................................................ 33

Auto-Negotiation: Parallel Detection ...................................................................... 34

Auto-Negotiation: Remote Fault Signaling ............................................................. 35

Auto-Negotiation: Reset and Restart ..................................................................... 35

Auto-Negotiation: Progress Monitor ....................................................................... 36

ICS1893BF, Rev. E, 8/11/09

August, 2009

ICS1893BF Data Sheet Rev. E - Release

Table of Contents

Section

6.3

6.3.1

6.3.2

6.3.3

6.3.4

6.3.5

6.3.6

6.4

6.4.1

6.4.2

6.4.3

6.4.4

6.4.5

6.4.6

6.4.7

6.5

6.5.1

6.5.2

6.5.3

6.5.4

6.5.5

6.5.6

6.5.7

6.5.8

6.5.9

6.5.10

6.5.11

6.5.12

6.5.13

6.5.14

6.6

6.6.1

6.6.2

Title

Page

Functional Block: 100Base-X PCS and PMA Sublayers ........................................ 36

PCS Sublayer ........................................................................................................ 36

PMA Sublayer ........................................................................................................ 36

PCS/PMA Transmit Modules ................................................................................. 37

PCS/PMA Receive Modules .................................................................................. 37

PCS Control Signal Generation ............................................................................. 38

4B/5B Encoding/Decoding ..................................................................................... 39

Functional Block: 100Base-TX TP-PMD Operations ............................................. 39

100Base-TX Operation: Stream Cipher Scrambler/Descrambler .......................... 39

100Base-TX Operation: MLT-3 Encoder/Decoder ................................................. 40

100Base-TX Operation: DC Restoration ................................................................ 40

100Base-TX Operation: Adaptive Equalizer .......................................................... 40

100Base-TX Operation: Twisted-Pair Transmitter ................................................. 40

100Base-TX Operation: Twisted-Pair Receiver ..................................................... 41

100Base-TX Operation: Isolation Transformer ...................................................... 41

Functional Block: 10Base-T Operations ................................................................ 41

10Base-T Operation: Manchester Encoder/Decoder ............................................. 41

10Base-T Operation: Clock Synthesis ................................................................... 42

10Base-T Operation: Clock Recovery ................................................................... 42

10Base-T Operation: Idle ....................................................................................... 42

10Base-T Operation: Link Monitor ......................................................................... 42

10Base-T Operation: Smart Squelch ..................................................................... 43

10Base-T Operation: Carrier Detection .................................................................44

10Base-T Operation: Collision Detection ............................................................... 44

10Base-T Operation: Jabber .................................................................................. 44

10Base-T Operation: SQE Test ............................................................................. 44

10Base-T Operation: Twisted-Pair Transmitter ..................................................... 45

10Base-T Operation: Twisted-Pair Receiver ......................................................... 45

10Base-T Operation: Auto Polarity Correction ....................................................... 45

10Base-T Operation: Isolation Transformer ........................................................... 46

Functional Block: Management Interface ............................................................... 46

Management Register Set Summary ..................................................................... 46

Management Frame Structure ............................................................................... 46

ICS1893BF, Rev. E, 8/11/09

August, 2009

ICS1893BF Data Sheet - Release

Table of Contents

Section

Chapter 7

7.1

7.1.1

7.1.2

7.1.3

7.1.4

7.2

7.2.1

7.2.2

7.2.3

7.2.4

7.2.5

7.2.6

7.2.7

7.2.8

7.2.9

7.2.10

7.3

7.3.1

7.3.2

7.3.3

7.3.4

7.3.5

7.3.6

7.3.7

7.3.8

7.3.9

7.3.10

7.3.11

7.3.12

7.3.13

7.4

Title

Page

Management Register Set ............................................................................................... 49

Introduction to Management Register Set ............................................................. 50

Management Register Set Outline ......................................................................... 50

Management Register Bit Access .......................................................................... 51

Management Register Bit Default Values .............................................................. 51

Management Register Bit Special Functions ......................................................... 52

Reset (bit 0.15) ...................................................................................................... 53

Loopback Enable (bit 0.14) .................................................................................... 54

Data Rate Select (bit 0.13) ..................................................................................... 54

Auto-Negotiation Enable (bit 0.12) ......................................................................... 54

Low Power Mode (bit 0.11) .................................................................................... 55

Isolate (bit 0.10) ..................................................................................................... 55

Restart Auto-Negotiation (bit 0.9) .......................................................................... 55

Duplex Mode (bit 0.8) ............................................................................................. 56

Collision Test (bit 0.7) ............................................................................................ 56

IEEE Reserved Bits (bits 0.6:0) ............................................................................. 56

100Base-T4 (bit 1.15) ............................................................................................ 57

100Base-TX Full Duplex (bit 1.14) ......................................................................... 58

100Base-TX Half Duplex (bit 1.13) ........................................................................ 58

10Base-T Full Duplex (bit 1.12) ............................................................................. 58

10Base-T Half Duplex (bit 1.11) ............................................................................ 58

IEEE Reserved Bits (bits 1.10:7) ........................................................................... 59

MF Preamble Suppression (bit 1.6) ....................................................................... 59

Auto-Negotiation Complete (bit 1.5) ....................................................................... 59

Remote Fault (bit 1.4) ............................................................................................ 60

Auto-Negotiation Ability (bit 1.3) ............................................................................ 60

Link Status (bit 1.2) ................................................................................................ 60

Jabber Detect (bit 1.1) ........................................................................................... 61

Extended Capability (bit 1.0) .................................................................................. 61

ICS1893BF, Rev. E, 8/11/09

August, 2009

ICS1893BF Data Sheet Rev. E - Release

Table of Contents

Section

7.5

7.5.1

7.5.2

7.5.3

7.6

7.6.1

7.6.2

7.6.3

7.6.4

7.6.5

7.6.6

7.7

7.7.1

7.7.2

7.7.3

7.7.4

7.7.5

7.8

7.8.1

7.8.2

7.8.3

7.8.4

7.8.5

7.8.6

7.9

7.9.1

7.9.2

7.9.3

7.9.4

7.9.5

7.9.6

7.10

7.10.1

7.10.2

7.10.3

7.10.4

7.10.5

Title

Page

OUI bits 19-24 (bits 3.15:10) .................................................................................. 63

Manufacturer's Model Number (bits 3.9:4) ............................................................. 63

Revision Number (bits 3.3:0) ................................................................................. 63

Next Page (bit 4.15) ............................................................................................... 65

IEEE Reserved Bit (bit 4.14) .................................................................................. 66

Remote Fault (bit 4.13) .......................................................................................... 66

IEEE Reserved Bits (bits 4.12:10) ......................................................................... 66

Technology Ability Field (bits 4.9:5) ....................................................................... 67

Selector Field (Bits 4.4:0) ....................................................................................... 67

Next Page (bit 5.15) ............................................................................................... 68

Acknowledge (bit 5.14) .......................................................................................... 69

Remote Fault (bit 5.13) .......................................................................................... 69

Technology Ability Field (bits 5.12:5) ..................................................................... 69

Selector Field (bits 5.4:0) ....................................................................................... 69

IEEE Reserved Bits (bits 6.15:5) ........................................................................... 70

Parallel Detection Fault (bit 6.4) ............................................................................. 71

Link Partner Next Page Able (bit 6.3) .................................................................... 71

Next Page Able (bit 6.2) ......................................................................................... 71

Page Received (bit 6.1) ......................................................................................... 71

Link Partner Auto-Negotiation Able (bit 6.0) .......................................................... 71

Next Page (bit 7.15) ............................................................................................... 73

IEEE Reserved Bit (bit 7.14) .................................................................................. 73

Message Page (bit 7.13) ........................................................................................ 73

Acknowledge 2 (bit 7.12) ....................................................................................... 73

Toggle (bit 7.11) ..................................................................................................... 73

Message Code Field / Unformatted Code Field (bits 7.10:0) ................................. 73

Next Page (bit 8.15) ............................................................................................... 75

IEEE Reserved Bit (bit 8.14) .................................................................................. 75

Message Page (bit 8.13) ........................................................................................ 75

Acknowledge 2 (bit 8.12) ....................................................................................... 75

Message Code Field / Unformatted Code Field (bits 8.10:0) ................................. 75

ICS1893BF, Rev. E, 8/11/09

August, 2009

1893BFT Related Products

	1893BFT	1893BFIT	1893BFI	1893BF	1893BKIT	1893BKT
Description	Interface Circuit, 1-Trnsvr, CMOS, PDSO48, 0.300 INCH, SSOP-48	Interface Circuit, 1-Trnsvr, CMOS, PDSO48, 0.300 INCH, SSOP-48	Interface Circuit, 1-Trnsvr, CMOS, PDSO48, 0.300 INCH, SSOP-48	Interface Circuit, 1-Trnsvr, CMOS, PDSO48, 0.300 INCH, SSOP-48	Interface Circuit, 1-Trnsvr, CMOS, PQCC56, 8 X 8 MM, PLASTIC, M0-220VLLD-5, MLF2-56	Interface Circuit, 1-Trnsvr, CMOS, PQCC56, 8 X 8 MM, PLASTIC, M0-220VLLD-5, MLF2-56
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Parts packaging code	SSOP	SSOP	SSOP	SSOP	DFN	DFN
package instruction	0.300 INCH, SSOP-48	0.300 INCH, SSOP-48	0.300 INCH, SSOP-48	0.300 INCH, SSOP-48	HVQCCN, LCC56,.31SQ,20	HVQCCN, LCC56,.31SQ,20
Contacts	48	48	48	48	56	56
Reach Compliance Code	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant
data rate	100000 Mbps	100000 Mbps	100000 Mbps	100000 Mbps	100000 Mbps	100000 Mbps
JESD-30 code	R-PDSO-G48	R-PDSO-G48	R-PDSO-G48	R-PDSO-G48	S-PQCC-N56	S-PQCC-N56
JESD-609 code	e0	e0	e0	e0	e0	e0
length	15.875 mm	15.875 mm	15.875 mm	15.875 mm	8 mm	8 mm
Humidity sensitivity level	1	1	1	1	3	3
Number of functions	1	1	1	1	1	1
Number of terminals	48	48	48	48	56	56
Transceiver quantity	1	1	1	1	1	1
Maximum operating temperature	70 °C	85 °C	85 °C	70 °C	85 °C	70 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SSOP	SSOP	SSOP	SSOP	HVQCCN	HVQCCN
Encapsulate equivalent code	SSOP48,.4	SSOP48,.4	SSOP48,.4	SSOP48,.4	LCC56,.31SQ,20	LCC56,.31SQ,20
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	SQUARE	SQUARE
Package form	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	225	225	225	225	240	240
power supply	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	2.8 mm	2.8 mm	2.8 mm	2.8 mm	1 mm	1 mm
Maximum slew rate	0.16 mA	0.16 mA	0.16 mA	0.16 mA	0.16 mA	0.16 mA
Nominal supply voltage	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Telecom integrated circuit types	INTERFACE CIRCUIT	INTERFACE CIRCUIT	INTERFACE CIRCUIT	INTERFACE CIRCUIT	INTERFACE CIRCUIT	INTERFACE CIRCUIT
Temperature level	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	NO LEAD	NO LEAD
Terminal pitch	0.635 mm	0.635 mm	0.635 mm	0.635 mm	0.5 mm	0.5 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	QUAD	QUAD
Maximum time at peak reflow temperature	20	20	20	20	NOT SPECIFIED	NOT SPECIFIED
width	7.5 mm	7.5 mm	7.5 mm	7.5 mm	8 mm	8 mm
Base Number Matches	1	1	1	1	1	1

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