NAND02GR4B2CZA1 datasheet, PDF

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NAND02GR4B2CZA1: Description128M X 8 FLASH 3V PROM, 35 ns, PDSO48; Categorystorage; File Size402KB，64 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/

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NAND02GR4B2CZA1 Overview

128M X 8 FLASH 3V PROM, 35 ns, PDSO48

NAND02GR4B2CZA1 Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	48
Minimum operating temperature	-40 Cel
Maximum operating temperature	85 Cel
Rated supply voltage	3 V
Minimum supply/operating voltage	2.7 V
Maximum supply/operating voltage	3.6 V
Processing package description	12 X 20 MM, PLASTIC, TSOP-48
state	Contact Mfr
ccess_time_max	35 ns
jesd_30_code	R-PDSO-G48
jesd_609_code	e0
storage density	1.02E9 bit
Memory IC type	FLASH
memory width	8
moisture_sensitivity_level	NOT SPECIFIED
Number of digits	1.28E8 words
Number of digits	128M
operating mode	ASYNCHRONOUS
organize	128MX8
Packaging Materials	PLASTIC/EPOXY
ckage_code	TSOP1
packaging shape	RECTANGULAR
Package Size	SMALL OUTLINE, THIN PROFILE
serial parallel	PARALLEL
eak_reflow_temperature__cel_	NOT SPECIFIED
gramming_voltage__v_	3
qualification_status	COMMERCIAL
seated_height_max	1.2 mm
surface mount	YES
Temperature level	INDUSTRIAL
terminal coating	TIN LEAD
Terminal form	GULL WING
Terminal spacing	0.5000 mm
Terminal location	DUAL
ime_peak_reflow_temperature_max__s_	NOT SPECIFIED
length	18.4 mm
width	12 mm

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NAND01G-B

NAND02G-B

1 Gbit, 2 Gbit,

2112 Byte/1056 Word Page, 1.8V/3V, NAND Flash Memory

Feature summary

●

High Density NAND Flash memories

–

Up to 2 Gbit memory array

Up to 64Mbit spare area

Cost effective solutions for mass

storage applications

x8 or x16 bus width

Multiplexed Address/ Data

Pinout compatibility for all densities

FBGA

●

NAND interface

–

TSOP48 12 x 20mm

●

Supply voltage

–

1.8V device: V

= 1.7 to 1.95V

3.0V device: V

= 2.7 to 3.6V

x8 device: (2048 + 64 spare) Bytes

x16 device: (1024 + 32 spare) Words

x8 device: (128K + 4K spare) Bytes

x16 device: (64K + 2K spare) Words

Random access: 25µs (max)

Sequential access: 50ns (min)

Page program time: 300µs (typ)

■

●

Page size

–

VFBGA63 9.5 x 12 x 1mm

TFBGA63 9.5 x 12 x 1.2mm

●

Block size

–

Serial Number option

Data protection

–

Hardware and Software Block Locking

Hardware Program/Erase locked during

Power transitions

100,000 Program/Erase cycles

10 years Data Retention

●

Page Read/Program

–

●

Data integrity

–

●

Copy Back Program mode

–

Fast page copy without external

buffering

Internal Cache Register to improve the

program and read throughputs

Block erase time: 2ms (typ)

ECOPACK

packages

Development tools

–

Error Correction Code software and

hardware models

Bad Blocks Management and Wear

Leveling algorithms

File System OS Native reference

software

Hardware simulation models

●

Cache Program and Cache Read modes

–

●

Fast Block Erase

–

Status Register

Electronic Signature

Chip Enable ‘don’t care’

–

for simple interface with microcontroller

●

February 2006

Rev 4.0

1/64

www.st.com

NAND01G-B, NAND02G-B

Contents

Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.1

Bad blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

3.10

3.11

3.12

Inputs/Outputs (I/O0-I/O7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Inputs/Outputs (I/O8-I/O15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Read Enable (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Power-Up Read Enable, Lock/Unlock Enable (PRL) . . . . . . . . . . . . . . . . 18

Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Ready/Busy (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.1

4.2

4.3

4.4

4.5

4.6

Command Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Address Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.1

Read Memory Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.1.1

Random Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3/64

Contents

6.1.2

NAND01G-B, NAND02G-B

Page Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.2

6.3

Cache Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Page Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.3.1

6.3.2

Sequential Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Random Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.4

6.5

6.6

6.7

6.8

Copy Back Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Cache Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Block Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Read Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.8.1

6.8.2

6.8.3

6.8.4

6.8.5

6.8.6

Write Protection Bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

P/E/R Controller and Cache Ready/Busy Bit (SR6) . . . . . . . . . . . . . . . 33

P/E/R Controller Bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Cache Program Error Bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Error Bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

SR4, SR3 and SR2 are Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.9

Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.1

7.2

7.3

7.4

Blocks Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Blocks Unlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Blocks Lock-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Block Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8.1

8.2

8.3

8.4

8.5

8.6

Bad Block Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Block Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Garbage Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Error Correction Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Hardware Simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.6.1

8.6.2

Behavioral simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

IBIS simulations models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Program and Erase Times and Endurance cycles . . . . . . . . . . . . . . . . 44

4/64

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Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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