MX29F200T/B
2M-BIT [256Kx8/128Kx16] CMOS FLASH MEMORY
FEATURES
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5.0V±10% for read, erase and write operation
131072x16/262144x8 switchable
Fast access time: 55/70/90/120ns
Low power consumption
- 40mA maximum active current@5MHz
- 1uA typical standby current
Command register architecture
- Byte/Word Programming (7us/12us typical)
- Erase (16K-Bytex1, 8K-Bytex2, 32K-Bytex1, and
64K-Byte x3)
Auto Erase (chip) and Auto Program
- Automatically erase any combination of sectors or
the whole chip with Erase Suspend capability.
- Automatically program and verify data at specified
address
Status Reply
- Data polling & Toggle bit for detection of program
and erase cycle completion.
Ready/Busy pin(RY/BY)
- Provides a hardware method or detecting program
or erase cycle completion
Compatibility with JEDEC standard
- Pinout and software compatible with single-power
supply Flash
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- Superior inadvertent write protection
Sector protection
- Hardware method to disable any combination of
sectors from program or erase operations
- Sector protect/unprotect for 5V only system or 5V/
12V system
100,000 minimum erase/program cycles
Latch-up protected to 100mA from -1V to VCC+1V
Boot Code Sector Architecture
- T = Top Boot Sector
- B = Bottom Boot Sector
Low VCC write inhibit is equal to or less than 3.2V
Package type:
- 44-pin SOP
- 48-pin TSOP
Erase suspend/ Erase Resume
- Suspends an erase operation to read data from, or
program data to a sector that is not being erased, then
resume the erase operation.
Hardware RESET pin
- Resets internal state mechine to the read mode
20 years data retention
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GENERAL DESCRIPTION
The MX29F200T/B is a 2-mega bit, single 5 Volt Flash
memory organized as 1M word x16 or 2M bytex8 MXIC's
Flash memories offer the most cost-effective and reli-
able read/write non-volatile random access memory.
The MX29F200T/B is packaged in 44-pin SOP and 48-
pin TSOP. It is designed to be reprogrammed and
erased in-system or in-standard EPROM programmers.
The standard MX29F200T/B offers access time as fast
as 55ns, allowing operation of high-speed microproces-
sors without wait states. To eliminate bus contention, the
MX29F200T/B has separate chip enable (CE) and output
enable (OE ) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29F200T/B uses a command register to manage this
functionality. The command register allows for 100%
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining maxi-
mum EPROM compatibility.
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields for
erase and programming operations produces reliable
cycling. The MX29F200T/B uses a 5.0V
±
10% VCC
supply to perform the High Reliability Erase and auto
Program/Erase algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up
protection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
P/N:PM0549
REV. 1.3, DEC. 24, 2001
1
MX29F200T/B
PIN CONFIGURATIONS
44 SOP(500mil)
NC
RY/BY
NC
A7
A6
A5
A4
A3
A2
A1
A0
CE
GND
OE
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RESET
WE
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
48 TSOP(TYPE I) (12mm x 20mm)
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
NC
RY/BY
NC
NC
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE
GND
CE
A0
MX29F200T/B
MX29F200T/B
(NORMAL TYPE)
A16
BYTE
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE
GND
CE
A0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
MX29F200T/B
(REVERSE TYPE)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
NC
RY/BY
NC
NC
A7
A6
A5
A4
A3
A2
A1
PIN DESCRIPTION
SYMBOL
A0-A16
Q0-Q14
Q15/A-1
CE
OE
RESET
WE
RY/BY
BYTE
VCC
GND
NC
PIN NAME
Address Input
Data Input/Output
Q15(Word mode)/LSB addr.(Byte mode)
Chip Enable Input
Output Enable Input
Hardware Reset Pin, Active low
Write Enable Input
Read/Busy Output
Word/Byte Selection Input
Power Supply Pin (+5V)
Ground Pin
Pin Not Connected Internally
P/N:PM0549
REV. 1.3 , DEC. 24, 2001
2
MX29F200T/B
SECTOR STRUCTURE
MX29F200T Top Boot Sector Addresses Tables
Sector Size Address Range (in hexadecimal)
(Kbytes/
A16
A15
A14
A13
A12
Kwords)
(x8)Address Range
(x16) Address Range
SA0
SA1
SA2
SA3
SA4
SA5
SA6
0
0
1
1
1
1
1
0
1
0
1
1
1
1
X
X
X
0
1
1
1
X
X
X
X
0
0
1
X
X
X
X
0
1
X
64/32
64/32
64/32
32/16
8/4
8/4
16/8
00000h-0FFFFh
10000h-1FFFFh
20000h-2FFFFh
30000h-37FFFh
38000h-39FFFh
3A000h-3BFFFh
3C000h-3FFFFh
00000h-07FFFh
08000h-0FFFFh
10000h-17FFFh
18000h-1BFFFh
1C000h-1CFFFh
1D000h-1DFFFh
1E000h-1FFFFh
MX29F200B Bottom Boot Sector Addresses Tables
Sector Size
(Kbytes/
A16
A15
A14
A13
A12
Kwords)
(x8)Address Range
(x16) Address Range
Address Range (in hexadecimal)
SA0
SA1
SA2
SA3
SA4
SA5
SA6
0
0
0
0
0
1
1
0
0
0
0
1
0
1
0
0
0
1
X
X
X
0
1
1
X
X
X
X
X
0
1
X
X
X
X
16/8
8/4
8/4
32/16
64/32
64/32
64/32
00000h-03FFFh
04000h-05FFFh
06000h-07FFFh
08000h-0FFFFh
10000h-1FFFFh
20000h-2FFFFh
30000h-3FFFFh
00000h-01FFFh
02000h-02FFFh
03000h-03FFFh
04000h-07FFFh
08000h-0FFFFh
10000h-17FFFh
18000h-1FFFFh
P/N:PM0549
REV. 1.3 , DEC. 24, 2001
3
MX29F200T/B
BLOCK DIAGRAM
WRITE
CE
OE
WE
CONTROL
INPUT
LOGIC
HIGH VOLTAGE
MACHINE
(WSM)
PROGRAM/ERASE
STATE
X-DECODER
MX29F200T/B
FLASH
ARRAY
ARRAY
STATE
REGISTER
ADDRESS
LATCH
A0-A16
AND
BUFFER
SENSE
AMPLIFIER
A-1/Q15
Y-DECODER
Y-PASS GATE
SOURCE
HV
COMMAND
DATA
DECODER
PGM
DATA
HV
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
Q0-Q14
I/O BUFFER
P/N:PM0549
REV. 1.3 , DEC. 24, 2001
4
MX29F200T/B
AUTOMATIC PROGRAMMING
The MX29F200T/B is byte programmable using the
Automatic Programming algorithm. The Automatic Pro-
gramming algorithm does not require the system to time
out sequence or verify the data programmed. The
typical chip programming time of the MX29F200T/B at
room temperature is less than 2 seconds.
AUTOMATIC ERASE ALGORITHM
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stand-
ard microprocessor write timings. The device will auto-
matically pre-program and verify the entire array. Then
the device automatically times the erase pulse width,
verifies the erase and counts the number of sequences.
A status bit toggling between consecutive read cycles
provides feedback to the user as to the status of the
programming operation.
Register contents serve as inputs to an internal state-
machine which controls the erase and programming
circuitry. During write cycles, the command register
internally latches addresses and data needed for the
programming and erase operations. During a system
write cycle, addresses are latched on the falling edge,
and data are latched on the rising edge of WE .
MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality,
reliability, and cost effectiveness. The MX29F200T/B
electrically erases all bits simultaneously using Fowler-
Nordheim tunneling. The bytes are programmed by
using the EPROM programming mechanism of hot
electron injection.
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is complete,
the device stays in read mode. After the state machine
has completed its task, it will allow the command register
to respond to its full command set.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 10 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
Typical erasure at room temperature is accomplished in
less than two second. The Automatic Erase algorithm
automatically programs the entire array prior to electrical
erase. The timing and verification of electrical erase are
internally controlled by the device.
AUTOMATIC SECTOR ERASE
The MX29F200T/B is sector(s) erasable using MXIC's
Auto Sector Erase algorithm. Sector erase modes allow
sectors of the array to be erased in one erase cycle. The
Automatic Sector Erase algorithm automatically pro-
grams the specified sector(s) prior to electrical erase.
The timing and verification of electrical erase are inter-
nally controlled by the device.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm requires the
user to only write program set-up commands (include 2
unlock write cycle and A0H) and a program command
(program data and address). The device automatically
times the programming pulse width, verifies the pro-
gram, and counts the number of sequences. A status bit
similar to DATA polling and a status bit toggling between
consecutive read cycles, provides feedback to the user
as to the status of the programming operation.
P/N:PM0549
REV. 1.3 , DEC. 24, 2001
5
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