STM32H753xI
32-bit Arm
®
Cortex
®
-M7 480MHz MCUs, 2MB Flash,
1MB RAM, 46 com. and analog interfaces, crypto
Datasheet
-
production data
Features
Core
•
32-bit Arm
®
Cortex
®
-M7 core with double-
precision FPU and L1 cache: 16 Kbytes of data
and 16 Kbytes of instruction cache; frequency
up to 480 MHz, MPU, 1027 DMIPS/
2.14 DMIPS/MHz (Dhrystone 2.1), and DSP
instructions
LQFP100
(14 x 14 mm)
LQFP144
(20 x 20 mm)
LQFP176
(24 x 24 mm)
LQFP208
(28 x 28 mm)
FBGA
FBGA
TFBGA100
(8 x 8 mm)
(1)
TFBGA240+25
(14 x 14 mm)
UFBGA169
(7 x 7 mm)
UFBGA176+25
(10 x 10 mm)
Memories
•
2 Mbytes of Flash memory with read-while-
write support
•
1 Mbyte of RAM: 192 Kbytes of TCM RAM (inc.
64 Kbytes of ITCM RAM + 128 Kbytes of
DTCM RAM for time critical routines),
864 Kbytes of user SRAM, and 4 Kbytes of
SRAM in Backup domain
•
Dual mode Quad-SPI memory interface
running up to 133 MHz
•
Flexible external memory controller with up to
32-bit data bus: SRAM, PSRAM,
SDRAM/LPSDR SDRAM, NOR/NAND Flash
memory clocked up to 100 MHz in
Synchronous mode
•
CRC calculation unit
•
1.62 to 3.6 V application supply and I/Os
•
POR, PDR, PVD and BOR
•
Dedicated USB power embedding a 3.3 V
internal regulator to supply the internal PHYs
•
Embedded regulator (LDO) with configurable
scalable output to supply the digital circuitry
•
Voltage scaling in Run and Stop mode (6
configurable ranges)
•
Backup regulator (~0.9 V)
•
Voltage reference for analog peripheral/V
REF+
•
Low-power modes: Sleep, Stop, Standby and
V
BAT
supporting battery charging
Low-power consumption
•
V
BAT
battery operating mode with charging
capability
•
CPU and domain power state monitoring pins
•
2.95 µA in Standby mode (Backup SRAM OFF,
RTC/LSE ON)
Security
•
ROP, PC-ROP, active tamper, secure firmware
upgrade support, Secure access mode
General-purpose input/outputs
•
Up to 168 I/O ports with interrupt capability
Clock management
•
Internal oscillators: 64 MHz HSI, 48 MHz
HSI48, 4 MHz CSI, 32 kHz LSI
•
External oscillators: 4-48 MHz HSE,
32.768 kHz LSE
•
3× PLLs (1 for the system clock, 2 for kernel
clocks) with Fractional mode
Reset and power management
•
3 separate power domains which can be
independently clock-gated or switched off:
– D1: high-performance capabilities
– D2: communication peripherals and timers
– D3: reset/clock control/power management
April 2019
This is information on a product in full production.
DS12117 Rev 7
1/356
www.st.com
STM32H753xI
Interconnect matrix
•
•
3 bus matrices (1 AXI and 2 AHB)
Bridges (5× AHB2-APB, 2× AXI2-AHB)
•
Chrom-ART graphical hardware Accelerator™
(DMA2D) to reduce CPU load
•
Hardware JPEG Codec
4 DMA controllers to unload the CPU
•
1× high-speed master direct memory access
controller (MDMA) with linked list support
•
2× dual-port DMAs with FIFO
•
1× basic DMA with request router capabilities
Up to 22 timers and watchdogs
•
1× high-resolution timer (2.1 ns max
resolution)
•
2× 32-bit timers with up to 4 IC/OC/PWM or
pulse counter and quadrature (incremental)
encoder input (up to 240 MHz)
•
2× 16-bit advanced motor control timers (up to
240 MHz)
•
10× 16-bit general-purpose timers (up to
240 MHz)
•
5× 16-bit low-power timers (up to 240 MHz)
•
2× watchdogs (independent and window)
•
1× SysTick timer
•
RTC with sub-second accuracy and hardware
calendar
Up to 35 communication peripherals
•
4× I2Cs FM+ interfaces (SMBus/PMBus)
•
4× USARTs/4x UARTs (ISO7816 interface,
LIN, IrDA, up to 12.5 Mbit/s) and 1x LPUART
•
6× SPIs, 3 with muxed duplex I2S audio class
accuracy via internal audio PLL or external
clock, 1x I2S in LP domain (up to 150 MHz)
•
4x SAIs (serial audio interface)
•
SPDIFRX interface
•
SWPMI single-wire protocol master I/F
•
MDIO Slave interface
•
2× SD/SDIO/MMC interfaces (up to 125 MHz)
•
2× CAN controllers: 2 with CAN FD, 1 with
time-triggered CAN (TT-CAN)
•
2× USB OTG interfaces (1FS, 1HS/FS) crystal-
less solution with LPM and BCD
•
Ethernet MAC interface with DMA controller
•
HDMI-CEC
•
8- to 14-bit camera interface (up to 80 MHz)
Cryptographic acceleration
•
AES 128, 192, 256, TDES,
•
HASH (MD5, SHA-1, SHA-2), HMAC
•
True random number generators
Debug mode
•
SWD & JTAG interfaces
•
4-Kbyte Embedded Trace Buffer
96-bit unique ID
All packages are ECOPACK
®
2 compliant
Table 1. Device summary
Reference
Part number
11 analog peripherals
•
3× ADCs with 16-bit max. resolution (up to 36
channels, up to 3.6 MSPS)
•
1× temperature sensor
•
2× 12-bit D/A converters (1 MHz)
•
2× ultra-low-power comparators
•
2× operational amplifiers (7.3 MHz bandwidth)
•
1× digital filters for sigma delta modulator
(DFSDM) with 8 channels/4 filters
STM32H753VI, STM32H753ZI,
STM32H753xI STM32H753II, STM32H753BI,
STM32H753XI, STM32H753AI
Graphics
•
LCD-TFT controller up to XGA resolution
2/356
DS12117 Rev 7
STM32H753xI
Contents
Contents
1
2
3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1
3.2
3.3
Arm
®
Cortex
®
-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3.1
3.3.2
3.3.3
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Secure access mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4
3.5
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.5.1
3.5.2
3.5.3
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.6
3.7
Low-power strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.7.1
3.7.2
Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
System reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16
3.17
3.18
3.19
General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Bus-interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DMA controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Chrom-ART Accelerator™ (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 33
Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . . . . 33
Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 33
Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 34
Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
V
BAT
operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
DS12117 Rev 7
3/356
7
Contents
STM32H753xI
3.20
3.21
3.22
3.23
3.24
3.25
3.26
3.27
3.28
3.29
Digital-to-analog converters (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Ultra-low-power comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Operational amplifiers (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 37
Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
JPEG Codec (JPEG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Cryptographic acceleration (CRYP and HASH) . . . . . . . . . . . . . . . . . . . . 40
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.29.1
3.29.2
3.29.3
3.29.4
3.29.5
3.29.6
3.29.7
3.29.8
High-resolution timer (HRTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 43
General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5) . . . . 44
Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.30
3.31
3.32
3.33
3.34
3.35
3.36
3.37
3.38
3.39
3.40
3.41
3.42
3.43
3.44
Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 45
Inter-integrated circuit interface (I
2
C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Universal synchronous/asynchronous receiver transmitter (USART) . . . 46
Low-power universal asynchronous receiver transmitter (LPUART) . . . . 47
Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) . 48
Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
SPDIFRX Receiver Interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . 49
Single wire protocol master interface (SWPMI) . . . . . . . . . . . . . . . . . . . . 49
Management Data Input/Output (MDIO) slaves . . . . . . . . . . . . . . . . . . . . 50
SD/SDIO/MMC card host interfaces (SDMMC) . . . . . . . . . . . . . . . . . . . . 50
Controller area network (FDCAN1, FDCAN2) . . . . . . . . . . . . . . . . . . . . . 50
Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 51
Ethernet MAC interface with dedicated DMA controller (ETH) . . . . . . . . . 51
High-definition multimedia interface (HDMI)
- consumer electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4/356
DS12117 Rev 7
STM32H753xI
Contents
4
5
6
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Electrical characteristics (rev Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.2
6.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
6.3.10
6.3.11
6.3.12
6.3.13
6.3.14
6.3.15
6.3.16
6.3.17
6.3.18
6.3.19
6.3.20
6.3.21
6.3.22
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 108
Embedded reset and power control block characteristics . . . . . . . . . . 109
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 124
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 129
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 136
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Delay block (DLYB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
16-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 177
DS12117 Rev 7
5/356
7
京公网安备 11010802033920号
EEWORLD
