HD74HC78FP-EL datasheet, PDF - EEWORLD Datasheet

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HD74HC78FP-EL: DescriptionJ-K Flip-Flop, HC/UH Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO14, FP-14DA; Categorylogic logic; File Size58KB，10 Pages; ManufacturerHitachi （Renesas ）; Websitehttp://www.renesas.com/eng/

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HD74HC78FP-EL Overview

J-K Flip-Flop, HC/UH Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO14, FP-14DA

HD74HC78FP-EL Parametric

Parameter Name	Attribute value
Maker	Hitachi （Renesas ）
Parts packaging code	SOIC
package instruction	SOP,
Contacts	14
Reach Compliance Code	unknown
Is Samacsys	N
Other features	WITH INDIVIDUAL SET INPUTS
series	HC/UH
JESD-30 code	R-PDSO-G14
length	10.06 mm
Logic integrated circuit type	J-K FLIP-FLOP
Number of digits	2
Number of functions	1
Number of terminals	14
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output polarity	COMPLEMENTARY
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
propagation delay (tpd)	190 ns
Certification status	Not Qualified
Maximum seat height	2.2 mm
Maximum supply voltage (Vsup)	6 V
Minimum supply voltage (Vsup)	2 V
Nominal supply voltage (Vsup)	4.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Trigger type	NEGATIVE EDGE
width	5.5 mm
Base Number Matches	1

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HD74HC78

Dual J-K Flip-Flops (with Preset, Common Clear and

Common Clock)

Description

This flip-flop is edge sensitive to the clock input and change state on the negative transition of the clock

pulse. Each flip-flop has independent J, K, and preset inputs and Q and

outputs. Two flip-flops are

controlled by a common clear and a common clock. Preset and clear are independent of the clock and

accomplished by a low logic level on the corresponding input.

Features

•

High Speed Operation: t

(Clock to Q) = 20 ns typ (C

= 50 pF)

•

High Output Current: Fanout of 10 LSTTL Loads

•

Wide Operating Voltage: V

= 2 to 6 V

•

Low Input Current: 1 µA max

•

Low Quiescent Supply Current: I

(static) = 2 µA max (Ta = 25°C)

HD74HC78FP-EL Related Products

	HD74HC78FP-EL	HD74HC78P	HD74HC78RP-EL	HD74HC78FP	HD74HC78T	HD74HC78T-EL
Description	J-K Flip-Flop, HC/UH Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO14, FP-14DA	J-K Flip-Flop, HC/UH Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDIP14, DP-14	J-K Flip-Flop, HC/UH Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO14, FP-14DN	J-K Flip-Flop, HC/UH Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO14, FP-14DA	J-K Flip-Flop, HC/UH Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO14, TTP-14D	J-K Flip-Flop, HC/UH Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO14, TTP-14D
Maker	Hitachi （Renesas ）	Hitachi （Renesas ）	Hitachi （Renesas ）	Hitachi （Renesas ）	Hitachi （Renesas ）	Hitachi （Renesas ）
Parts packaging code	SOIC	DIP	SOIC	SOIC	SOIC	SOIC
package instruction	SOP,	DIP, DIP14,.3	SOP,	SOP, SOP14,.3	TSSOP, TSSOP14,.25	TSSOP,
Contacts	14	14	14	14	14	14
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown
series	HC/UH	HC/UH	HC/UH	HC/UH	HC/UH	HC/UH
JESD-30 code	R-PDSO-G14	R-PDIP-T14	R-PDSO-G14	R-PDSO-G14	R-PDSO-G14	R-PDSO-G14
length	10.06 mm	19.2 mm	8.65 mm	10.06 mm	5 mm	5 mm
Logic integrated circuit type	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP
Number of digits	2	2	2	2	2	2
Number of functions	1	1	1	1	1	1
Number of terminals	14	14	14	14	14	14
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
Output polarity	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	DIP	SOP	SOP	TSSOP	TSSOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	IN-LINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
propagation delay (tpd)	190 ns	190 ns	190 ns	190 ns	190 ns	190 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	2.2 mm	5.06 mm	1.75 mm	2.2 mm	1.1 mm	1.1 mm
Maximum supply voltage (Vsup)	6 V	6 V	6 V	6 V	6 V	6 V
Minimum supply voltage (Vsup)	2 V	2 V	2 V	2 V	2 V	2 V
Nominal supply voltage (Vsup)	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
surface mount	YES	NO	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	GULL WING	THROUGH-HOLE	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	1.27 mm	2.54 mm	1.27 mm	1.27 mm	0.65 mm	0.65 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Trigger type	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE
width	5.5 mm	7.62 mm	3.95 mm	5.5 mm	4.4 mm	4.4 mm
Other features	WITH INDIVIDUAL SET INPUTS	-	WITH INDIVIDUAL SET INPUTS	-	WITH INDIVIDUAL SET INPUTS	WITH INDIVIDUAL SET INPUTS

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Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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