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HD74HC78T

Description
J-K Flip-Flop, HC/UH Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO14, TTP-14D
Categorylogic    logic   
File Size58KB,10 Pages
ManufacturerHitachi (Renesas )
Websitehttp://www.renesas.com/eng/
Download Datasheet Parametric Compare View All

HD74HC78T Overview

J-K Flip-Flop, HC/UH Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO14, TTP-14D

HD74HC78T Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerHitachi (Renesas )
Parts packaging codeSOIC
package instructionTSSOP, TSSOP14,.25
Contacts14
Reach Compliance Codeunknown
Other featuresWITH INDIVIDUAL SET INPUTS
seriesHC/UH
JESD-30 codeR-PDSO-G14
JESD-609 codee0
length5 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeJ-K FLIP-FLOP
Maximum Frequency@Nom-Sup24000000 Hz
MaximumI(ol)0.004 A
Number of digits2
Number of functions1
Number of terminals14
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output polarityCOMPLEMENTARY
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP14,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
power supply2/6 V
propagation delay (tpd)190 ns
Certification statusNot Qualified
Maximum seat height1.1 mm
Maximum supply voltage (Vsup)6 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)4.5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Trigger typeNEGATIVE EDGE
width4.4 mm
HD74HC78
Dual J-K Flip-Flops (with Preset, Common Clear and
Common Clock)
Description
This flip-flop is edge sensitive to the clock input and change state on the negative transition of the clock
pulse. Each flip-flop has independent J, K, and preset inputs and Q and
Q
outputs. Two flip-flops are
controlled by a common clear and a common clock. Preset and clear are independent of the clock and
accomplished by a low logic level on the corresponding input.
Features
High Speed Operation: t
pd
(Clock to Q) = 20 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: V
CC
= 2 to 6 V
Low Input Current: 1 µA max
Low Quiescent Supply Current: I
CC
(static) = 2 µA max (Ta = 25°C)

HD74HC78T Related Products

HD74HC78T HD74HC78P HD74HC78FP-EL HD74HC78RP-EL HD74HC78FP HD74HC78T-EL
Description J-K Flip-Flop, HC/UH Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO14, TTP-14D J-K Flip-Flop, HC/UH Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDIP14, DP-14 J-K Flip-Flop, HC/UH Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO14, FP-14DA J-K Flip-Flop, HC/UH Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO14, FP-14DN J-K Flip-Flop, HC/UH Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO14, FP-14DA J-K Flip-Flop, HC/UH Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO14, TTP-14D
Maker Hitachi (Renesas ) Hitachi (Renesas ) Hitachi (Renesas ) Hitachi (Renesas ) Hitachi (Renesas ) Hitachi (Renesas )
Parts packaging code SOIC DIP SOIC SOIC SOIC SOIC
package instruction TSSOP, TSSOP14,.25 DIP, DIP14,.3 SOP, SOP, SOP, SOP14,.3 TSSOP,
Contacts 14 14 14 14 14 14
Reach Compliance Code unknown unknown unknown unknown unknown unknown
series HC/UH HC/UH HC/UH HC/UH HC/UH HC/UH
JESD-30 code R-PDSO-G14 R-PDIP-T14 R-PDSO-G14 R-PDSO-G14 R-PDSO-G14 R-PDSO-G14
length 5 mm 19.2 mm 10.06 mm 8.65 mm 10.06 mm 5 mm
Logic integrated circuit type J-K FLIP-FLOP J-K FLIP-FLOP J-K FLIP-FLOP J-K FLIP-FLOP J-K FLIP-FLOP J-K FLIP-FLOP
Number of digits 2 2 2 2 2 2
Number of functions 1 1 1 1 1 1
Number of terminals 14 14 14 14 14 14
Maximum operating temperature 85 °C 85 °C 85 °C 85 °C 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C
Output polarity COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP DIP SOP SOP SOP TSSOP
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH IN-LINE SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
propagation delay (tpd) 190 ns 190 ns 190 ns 190 ns 190 ns 190 ns
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height 1.1 mm 5.06 mm 2.2 mm 1.75 mm 2.2 mm 1.1 mm
Maximum supply voltage (Vsup) 6 V 6 V 6 V 6 V 6 V 6 V
Minimum supply voltage (Vsup) 2 V 2 V 2 V 2 V 2 V 2 V
Nominal supply voltage (Vsup) 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V
surface mount YES NO YES YES YES YES
technology CMOS CMOS CMOS CMOS CMOS CMOS
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL
Terminal form GULL WING THROUGH-HOLE GULL WING GULL WING GULL WING GULL WING
Terminal pitch 0.65 mm 2.54 mm 1.27 mm 1.27 mm 1.27 mm 0.65 mm
Terminal location DUAL DUAL DUAL DUAL DUAL DUAL
Trigger type NEGATIVE EDGE NEGATIVE EDGE NEGATIVE EDGE NEGATIVE EDGE NEGATIVE EDGE NEGATIVE EDGE
width 4.4 mm 7.62 mm 5.5 mm 3.95 mm 5.5 mm 4.4 mm
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