72281L20PFGI datasheet, PDF - EEWORLD Datasheet

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72281L20PFGI: DescriptionFIFO, 64KX9, 12ns, Synchronous, CMOS, PQFP64; Categorystorage storage; File Size227KB，26 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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72281L20PFGI Overview

FIFO, 64KX9, 12ns, Synchronous, CMOS, PQFP64

72281L20PFGI Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
package instruction	QFP, QFP64,.63SQ,32
Reach Compliance Code	compliant
ECCN code	EAR99
Is Samacsys	N
Maximum access time	12 ns
Maximum clock frequency (fCLK)	50 MHz
period time	20 ns
JESD-30 code	S-PQFP-G64
JESD-609 code	e3
memory density	589824 bit
Memory IC Type	OTHER FIFO
memory width	9
Humidity sensitivity level	3
Number of functions	1
Number of terminals	64
word count	65536 words
character code	64000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	64KX9
Exportable	YES
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Encapsulate equivalent code	QFP64,.63SQ,32
Package shape	SQUARE
Package form	FLATPACK
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	5 V
Certification status	Not Qualified
Maximum standby current	0.02 A
Maximum slew rate	0.08 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
Base Number Matches	1

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CMOS SuperSync FIFO™

65,536 x 9

131,072 x 9

FEATURES:

•

IDT72281

IDT72291

•

Choose among the following memory organizations:

IDT72281

65,536 x 9

IDT72291

131,072 x 9

Pin-compatible with the IDT72261LA/72271LA SuperSync FIFOs

10ns read/write cycle time (6.5ns access time)

Fixed, low first word data latency time

Auto power down minimizes standby power consumption

Master Reset clears entire FIFO

Partial Reset clears data, but retains programmable

settings

Retransmit operation with fixed, low first word data

latency time

Empty, Full and Half-Full flags signal FIFO status

Programmable Almost-Empty and Almost-Full flags, each flag

can default to one of two preselected offsets

Program partial flags by either serial or parallel means

Select IDT Standard timing (using

and

flags) or First

Word Fall Through timing (using

and

flags)

Output enable puts data outputs into high impedance state

Easily expandable in depth and width

Independent Read and Write clocks (permit reading and writing

simultaneously)

Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-

pin Slim Thin Quad Flat Pack (STQFP)

High-performance submicron CMOS technology

Industrial temperature range (-40°C to +85°C) is available

DESCRIPTION:

The IDT72281/72291 are exceptionally deep, high speed, CMOS First-In-

First-Out (FIFO) memories with clocked read and write controls. These FIFOs

offer numerous improvements over previous SuperSync FIFOs, including the

following:

•

The limitation of the frequency of one clock input with respect to the other has

been removed. The Frequency Select pin (FS) has been removed, thus

it is no longer necessary to select which of the two clock inputs, RCLK or

WCLK, is running at the higher frequency.

•

The period required by the retransmit operation is now fixed and short.

•

The first word data latency period, from the time the first word is written to an

empty FIFO to the time it can be read, is now fixed and short. (The variable

clock cycle counting delay associated with the latency period found on

previous SuperSync devices has been eliminated on this SuperSync family.)

SuperSync FIFOs are particularly appropriate for network, video, telecom-

munications, data communications and other applications that need to buffer

large amounts of data.

FUNCTIONAL BLOCK DIAGRAM

WEN

WCLK

-D

LD SEN

INPUT REGISTER

OFFSET REGISTER

FF/IR

PAF

EF/OR

PAE

FWFT/SI

WRITE CONTROL

LOGIC

RAM ARRAY

65,536 x 9

131,072 x 9

FLAG

LOGIC

WRITE POINTER

READ POINTER

READ

CONTROL

LOGIC

OUTPUT REGISTER

MRS

PRS

RESET

LOGIC

RCLK

REN

-Q

4675 drw01

IDT, IDT logo are registered trademarks of Integrated Device Technology, Inc. The SuperSync FIFO is a trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

2009

JANUARY 2009

DSC-4675/4

72281L20PFGI Related Products

	72281L20PFGI	72281L20TFGI	72291L20PFG	72291L20PFGI	72291L20TFG	72291L20TFGI	72281L20PFG	72281L20TFG
Description	FIFO, 64KX9, 12ns, Synchronous, CMOS, PQFP64	FIFO, 64KX9, 12ns, Synchronous, CMOS, PQFP64, GREEN, STQFP-64	FIFO, 128KX9, 12ns, Synchronous, CMOS, PQFP64, GREEN, PLASTIC, TQFP-64	FIFO, 128KX9, 12ns, Synchronous, CMOS, PQFP64	FIFO, 128KX9, 12ns, Synchronous, CMOS, PQFP64, GREEN, STQFP-64	FIFO, 128KX9, 12ns, Synchronous, CMOS, PQFP64, GREEN, STQFP-64	FIFO, 64KX9, 12ns, Synchronous, CMOS, PQFP64, GREEN, PLASTIC, TQFP-64	FIFO, 64KX9, 12ns, Synchronous, CMOS, PQFP64, GREEN, STQFP-64
Is it lead-free?	Lead free	Lead free	Lead free	Lead free	Lead free	Lead free	Lead free	Lead free
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to	conform to	conform to	conform to
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
package instruction	QFP, QFP64,.63SQ,32	LFQFP, QFP64,.47SQ,20	LQFP, QFP64,.63SQ,32	QFP, QFP64,.63SQ,32	LFQFP, QFP64,.47SQ,20	LFQFP, QFP64,.47SQ,20	LQFP, QFP64,.63SQ,32	LFQFP, QFP64,.47SQ,20
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
Maximum access time	12 ns	12 ns	12 ns	12 ns	12 ns	12 ns	12 ns	12 ns
Maximum clock frequency (fCLK)	50 MHz	50 MHz	50 MHz	50 MHz	50 MHz	50 MHz	50 MHz	50 MHz
period time	20 ns	20 ns	20 ns	20 ns	20 ns	20 ns	20 ns	20 ns
JESD-30 code	S-PQFP-G64	S-PQFP-G64	S-PQFP-G64	S-PQFP-G64	S-PQFP-G64	S-PQFP-G64	S-PQFP-G64	S-PQFP-G64
JESD-609 code	e3	e3	e3	e3	e3	e3	e3	e3
memory density	589824 bit	589824 bit	1179648 bit	1179648 bit	1179648 bit	1179648 bit	589824 bit	589824 bit
Memory IC Type	OTHER FIFO	OTHER FIFO	OTHER FIFO	OTHER FIFO	OTHER FIFO	OTHER FIFO	OTHER FIFO	OTHER FIFO
memory width	9	9	9	9	9	9	9	9
Humidity sensitivity level	3	3	3	3	3	3	3	3
Number of functions	1	1	1	1	1	1	1	1
Number of terminals	64	64	64	64	64	64	64	64
word count	65536 words	65536 words	131072 words	131072 words	131072 words	131072 words	65536 words	65536 words
character code	64000	64000	128000	128000	128000	128000	64000	64000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	85 °C	70 °C	85 °C	70 °C	85 °C	70 °C	70 °C
organize	64KX9	64KX9	128KX9	128KX9	128KX9	128KX9	64KX9	64KX9
Exportable	YES	YES	YES	YES	YES	YES	YES	YES
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QFP	LFQFP	LQFP	QFP	LFQFP	LFQFP	LQFP	LFQFP
Encapsulate equivalent code	QFP64,.63SQ,32	QFP64,.47SQ,20	QFP64,.63SQ,32	QFP64,.63SQ,32	QFP64,.47SQ,20	QFP64,.47SQ,20	QFP64,.63SQ,32	QFP64,.47SQ,20
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	FLATPACK	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE	FLATPACK	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE, FINE PITCH
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	260	260	260	260	260	260	260	260
power supply	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum standby current	0.02 A	0.02 A	0.02 A	0.02 A	0.02 A	0.02 A	0.02 A	0.02 A
Maximum slew rate	0.08 mA	0.08 mA	0.08 mA	0.08 mA	0.08 mA	0.08 mA	0.08 mA	0.08 mA
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Matte Tin (Sn)	Matte Tin (Sn) - annealed	Matte Tin (Sn)	Matte Tin (Sn)	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed	Matte Tin (Sn)	Matte Tin (Sn) - annealed
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.8 mm	0.5 mm	0.8 mm	0.8 mm	0.5 mm	0.5 mm	0.8 mm	0.5 mm
Terminal location	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	30	30	30	30	30	30	30	30
Base Number Matches	1	1	1	1	1	1	1	1
Is Samacsys	N	-	N	N	N	N	N	-
Parts packaging code	-	QFP	QFP	-	QFP	QFP	QFP	QFP
Contacts	-	64	64	-	64	64	64	64
Other features	-	RETRANSMIT; AUTO POWER DOWN; EASY EXPANDABLE IN DEPTH AND WIDTH	RETRANSMIT; AUTO POWER DOWN; EASY EXPANDABLE IN DEPTH AND WIDTH	-	RETRANSMIT; AUTO POWER DOWN; EASY EXPANDABLE IN DEPTH AND WIDTH	RETRANSMIT; AUTO POWER DOWN; EASY EXPANDABLE IN DEPTH AND WIDTH	RETRANSMIT; AUTO POWER DOWN; EASY EXPANDABLE IN DEPTH AND WIDTH	RETRANSMIT; AUTO POWER DOWN; EASY EXPANDABLE IN DEPTH AND WIDTH
length	-	10 mm	14 mm	-	10 mm	10 mm	14 mm	10 mm
Maximum seat height	-	1.6 mm	1.6 mm	-	1.6 mm	1.6 mm	1.6 mm	1.6 mm
width	-	10 mm	14 mm	-	10 mm	10 mm	14 mm	10 mm

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