MTD2955V
Power MOSFET 12 A, 60 V
P−Channel DPAK
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and power
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected voltage
transients.
Features
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12 A, 60 V
R
DS(on)
= 185 mW (Typ)
•
Avalanche Energy Specified
•
I
DSS
and V
DS(on)
Specified at Elevated Temperature
•
Pb−Free Packages are Available
MAXIMUM RATINGS
(T
C
= 25°C unless otherwise noted)
Rating
Drain−to−Source Voltage
Drain−to−Gate Voltage (R
GS
= 1.0 MW)
Gate−to−Source Voltage
−
Continuous
−
Non−repetitive (t
p
≤
10 ms)
Drain Current
−
Continuous
Drain Current
−
Continuous @ 100°C
Drain Current
−
Single Pulse (t
p
≤
10
ms)
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ 25°C (Note 2)
Operating and Storage Temperature
Range
Single Pulse Drain−to−Source Avalanche
Energy
−
Starting T
J
= 25°C
(V
DD
= 25 Vdc, V
GS
= 10 Vdc, Peak
I
L
= 12 Apk, L = 3.0 mH, R
G
= 25
W)
Thermal Resistance
−
Junction to Case
−
Junction to Ambient (Note 1)
−
Junction to Ambient (Note 2)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10
seconds
Symbol
V
DSS
V
DGR
V
GS
V
GSM
I
D
I
D
Value
60
60
±
20
±
25
12
8.0
42
60
0.4
2.1
−55
to
175
216
Unit
Vdc
Vdc
G
P−Channel
D
S
Vdc
Vpk
Adc
Apk
Watts
W/°C
Watts
°C
mJ
4
DPAK−3
CASE 369D
STYLE 2
2
3
1 2
4
DPAK−3
CASE 369C
STYLE 2
I
DM
P
D
3
T
J
, T
stg
E
AS
R
qJC
R
qJA
R
qJA
T
L
2.5
100
71.4
260
°C/W
1
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. When surface mounted to an FR4 board using the minimum recommended
pad size.
2. When surface mounted to an FR4 board using the 0.5 sq.in. pad size.
ORDERING INFORMATION
See detailed ordering and shipping information in the
package dimensions section on page 7 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 7 of this data sheet.
©
Semiconductor Components Industries, LLC, 2006
August, 2006
−
Rev. 8
1
Publication Order Number:
MTD2955V/D
MTD2955V
ELECTRICAL CHARACTERISTICS
(T
J
= 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(V
GS
= 0 Vdc, I
D
= 0.25 mAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(V
DS
= 60 Vdc, V
GS
= 0 Vdc)
(V
DS
= 60 Vdc, V
GS
= 0 Vdc, T
J
= 150°C)
Gate−Body Leakage Current (V
GS
=
±
20 Vdc, V
DS
= 0 Vdc)
ON CHARACTERISTICS
(Note 3)
Gate Threshold Voltage
(V
DS
= V
GS
, I
D
= 250
mAdc)
Threshold Temperature Coefficient (Negative)
Static Drain−to−Source On−Resistance
(V
GS
= 10 Vdc, I
D
= 6.0 Adc)
Drain−to−Source On−Voltage
(V
GS
= 10 Vdc, I
D
= 12 Adc)
(V
GS
= 10 Vdc, I
D
= 6.0 Adc, T
J
= 150°C)
Forward Transconductance (V
DS
= 10 Vdc, I
D
= 6.0 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS
(Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Gate Charge
(V
DS
= 48 Vdc, I
D
= 12 Adc,
V
GS
= 10 Vdc)
(V
DD
= 30 Vdc, I
D
= 12 Adc,
V
GS
= 10 Vdc,
R
G
= 9.1
W)
t
d(on)
t
r
t
d(off)
t
f
Q
T
Q
1
Q
2
Q
3
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage (Note 3)
(I
S
= 12 Adc, V
GS
= 0 Vdc)
(I
S
= 12 Adc, V
GS
= 0 Vdc, T
J
= 150°C)
V
SD
−
−
−
−
−
−
1.8
1.5
115
90
25
0.53
3.0
−
−
−
−
−
mC
Vdc
−
−
−
−
−
−
−
−
15
50
24
39
19
4.0
9.0
7.0
30
100
50
80
30
−
−
−
nC
ns
(V
DS
= 25 Vdc, V
GS
= 0 Vdc,
f = 1.0 MHz)
C
iss
C
oss
C
rss
−
−
−
550
200
50
770
280
100
pF
(Cpk
≥
2.0) (Note 5)
V
GS(th)
2.0
−
−
−
−
3.0
2.8
5.0
0.185
−
−
5.0
4.0
−
0.230
2.9
2.5
−
Vdc
mV/°C
W
Vdc
(Cpk
≥
2.0) (Note 5)
V
(BR)DSS
60
−
−
−
−
−
58
−
−
−
−
−
10
100
100
Vdc
mV/°C
mAdc
Symbol
Min
Typ
Max
Unit
I
DSS
I
GSS
nAdc
(Cpk
≥
1.5) (Note 5)
R
DS(on)
V
DS(on)
g
FS
mhos
Reverse Recovery Time
(I
S
= 12 Adc, V
GS
= 0 Vdc,
dI
S
/dt = 100 A/ms)
Reverse Recovery Stored
Charge
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
3. Pulse Test: Pulse Width
≤
300
ms,
Duty Cycle
≤
2%.
4. Switching characteristics are independent of operating junction temperature.
Max limit
−
Typ
5. Reflects typical values.
C
pk
=
3 x SIGMA
t
rr
t
a
t
b
Q
RR
ns
L
D
−
−
−
3.5
4.5
7.5
−
−
−
nH
L
S
nH
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MTD2955V
TYPICAL ELECTRICAL CHARACTERISTICS
25
I D , DRAIN CURRENT (AMPS)
24
9V
8V
I D , DRAIN CURRENT (AMPS)
21
18
15
12
9
6
3
10
0
2
3
5
7
9
4
6
8
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
10
T
J
= 25°C
V
GS
= 10 V
V
DS
≥
10 V
T
J
= − 55°C
100°C
25°C
20
7V
15
10
6V
5
0
5V
0
1
3
4
5
6
7
8
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
2
9
Figure 1. On−Region Characteristics
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0
3
6
9
15
18
12
I
D
, DRAIN CURRENT (AMPS)
21
24
25°C
− 55°C
V
GS
= 10 V
T
J
= 100°C
0.250
T
J
= 25°C
V
GS
= 10 V
0.225
0.200
0.175
0.150
0.125
0.100
0.075
0.050
0
3
6
15 V
9
18
12
15
I
D
, DRAIN CURRENT (AMPS)
21
24
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
RDS(on) , DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
− 50
− 25
0
25
50
75
100 125
T
J
, JUNCTION TEMPERATURE (°C)
150
175
V
GS
= 10 V
I
D
= 6 A
I DSS , LEAKAGE (nA)
1000
V
GS
= 0 V
T
J
= 125°C
100
100°C
10
0
10
30
40
20
50
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
60
Figure 5. On−Resistance Variation with
Temperature
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Figure 6. Drain−To−Source Leakage
Current versus Voltage
MTD2955V
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
G(AV)
) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V
GS
remains virtually constant at a level
known as the plateau voltage, V
SGP
. Therefore, rise and fall
times may be approximated by the following:
t
r
= Q
2
x R
G
/(V
GG
−
V
GSP
)
t
f
= Q
2
x R
G
/V
GSP
where
V
GG
= the gate drive voltage, which varies from zero to V
GG
R
G
= the gate drive resistance
and Q
2
and V
GSP
are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
= R
G
C
iss
In [V
GG
/(V
GG
−
V
GSP
)]
t
d(off)
= R
G
C
iss
In (V
GG
/V
GSP
)
1800
1600
C, CAPACITANCE (pF)
1400
1200
1000
800
600
400
200
0
10
5
V
GS
0
V
DS
5
10
C
iss
C
oss
C
rss
15
20
25
C
rss
C
iss
V
DS
= 0 V
V
GS
= 0 V
The capacitance (C
iss
) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating t
d(on)
and is read at a voltage corresponding to the
on−state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
T
J
= 25°C
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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MTD2955V
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
10
9
8
7
6
5
4
3
2
1
0
0
2
Q3
4
6
8
10
12
14
V
DS
16
18
Q
T
, TOTAL CHARGE (nC)
Q1
Q2
V
GS
QT
30
27
24
21
18
15
12
I
D
= 12 A 9
T
J
= 25°C 6
3
0
20
1000
VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V
DD
= 30 V
I
D
= 12 A
V
GS
= 10 V
T
J
= 25°C
t
r
t
f
t, TIME (ns)
100
10
t
d(off)
t
d(on)
1
1
10
R
G
, GATE RESISTANCE (OHMS)
100
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
12
11
I S , SOURCE CURRENT (AMPS)
10
9
8
7
6
5
4
3
2
1
0
0.5
V
GS
= 0 V
T
J
= 25°C
0.7
0.9
1.1
1.3
1.5
1.7
1.9
V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (T
C
) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed
in
AN569,
“Transient
Thermal
Resistance−General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(I
DM
) nor rated voltage (V
DSS
) is exceeded and the
transition time (t
r
,t
f
) do not exceed 10
ms.
In addition the total
power averaged over a complete switching cycle must not
exceed (T
J(MAX)
−
T
C
)/(R
qJC
).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (I
DM
), the energy rating is specified at rated
continuous current (I
D
), in accordance with industry
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 12). Maximum
energy at currents below rated continuous I
D
can safely be
assumed to equal the values indicated.
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